MT8972BE datasheet(7/20 Pages) MITEL

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MT8971B/72B

9-113

the Precan pin high. This mode simplifies the design

of external line transceivers used for loop extension

applications.

The Precan pin features an internal

pull-down

which

allows

this

left

unconnected in applications where this function is

not required. The resultant signal passes through

a receive filter to bandlimit and equalize it. At this

point, the echo estimate from the echo canceller is

subtracted from the precancelled received signal.

This difference signal is then input to the echo

canceller as an error signal and also squared up by a

comparator and passed to the biphase receiver.

Within the echo canceller, the sign of this error signal

is determined.

Depending on the sign, the echo

estimate is either incremented or decremented and

this new estimate is stored back in RAM.

The

timebase

both

SLV

and

MAS

modes

(generated internally in SLV mode and externally in

MAS mode) is phase-locked to the received data

stream.

This phase-locked clock operates the

Biphase Decoder, Descrambler and Deprescrambler

in MAS mode and the entire chip in SLV mode. The

Biphase Decoder decodes the received encoded bit

stream resulting in the original NRZ data which is

passed onto the Descrambler and Deprescrambler

where the data is restored to its original content by

performing the reverse polynomials. The SYNC bits

are extracted and the Receive Interface separates

the channels and outputs them to the proper ports in

the proper channel times.

The destination of the

various channels is the same as that received on the

input DV and CD ports.

The Transmit/Receive Timing and Control block

generates all the clocks for the transmit and receive

functions and controls the entire chip according to

the control register.

In order that more than one

DNIC may be connected to the same DV and

CD ports an F0o signal is generated which signals

the next device in a daisy chain that its channel

times are now active.

In this arrangement only

the first DNIC in the chain receives the system F0

with the following devices receiving its predecessor’s

F0o.

In MOD mode, all the ports have a different format.

The line port again operates at 80 or 160 kbit/s,

however, there is no synchronization overhead, only

transparent data. The DV and CD ports carry serial

data at 80 or 160 kbit/s with the DV port transferring

all the data for the line and the CD port carrying the

C-channel only. In this mode the transfer of data at

both ports is synchronized to the TCK and RCK

clocks for transmit and receive data, respectively.

The CLD signal goes low to indicate the start of the

C-channel data on the CD port. It is used to load and

latch the input and output C-channel but has no

relationship to the data on the DV port.

Operating Modes (MS0-2)

The logic levels present on the mode select pins

MS0, MS1 and MS2 program the DNIC for different

operating modes and configure the DV and CD ports

accordingly.

Table

shows

the

modes

corresponding to the state of MS0-2.

These pins

select the DNIC to operate as a MASTER or SLAVE,

in DUAL or SINGLE port operation, in MODEM or

DIGITAL NETWORK mode and the order of the C

and D channels on the CD port. Table 2 provides a

description of each mode and Table 3 gives a pin

configuration according to the mode selected for all

pins that have variable functions.

These functions

vary depending on whether it is in MAS or SLV, and

whether DN or MOD mode is used.

The overall mode of operation of the DNIC can be

programmed

to be

either

baseband

modem

(MOD mode)

or a digital network transceiver (DN

mode).

As a baseband modem, transmit/receive

data is passed transparently through the device at 80

or 160 kbit/s by the DV port. The CD port transfers

the C-channel and D-Channel also at

80 or 160

kbit/s.

In DN mode, both the DV and CD ports operate as

ST-BUS streams at 2.048 Mbit/s.

The DV port

transfers data over pins DSTi and DSTo while on the

Table 1. Mode Select Pins

E=Enabled

X=Not Applicable

Blanks are disabled

Mode Select Pins

Mode

Operating Mode

MS2

MS1

MS0

SLV

MAS

DUAL

SINGL

MOD

D-C

C-D

ODE

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