MT8972BE datasheet(3/20 Pages) MITEL

3 / 20 page

MT8971B/72B

9-109

Figure 3 - DV Port - 80 kbit/s (Modes 2, 3, 6)

Figure 4 - DV Port - 160 kbit/s (Modes 2, 3, 6)

OSC1

Oscillator Input. CMOS Input. D.C. couple signals to this pin. Refer to D.C. Electrical

Characteristics for OSC1 input requirements.

Precan

Precanceller Disable. When held to Logic ’1’, the internal path from LOUT to the

precanceller is forced to VBias thus bypassing the precanceller section. When logic ’0’, the

LOUT to the precanceller path is enabled and functions normally. An internal pulldown (50

Ω) is provided on this pin.

1,6,

11,

18,

20,

No Connection. Leave open circuit.

LOUT DIS LOUT Disable. When held to logic “1”, LOUT is disabled (i.e., output = VBias). When logic

“0”, LOUT functions normally. An internal pulldown (50 kΩ) is provided on this pin.

TEST

Test Pin.

Connect to VSS for normal operation.

LIN

Receive Signal input (Analog).

VDD

Positive Power Supply (+5V) input.

Pin Description (continued)

Pin #

Name

Description

DIP PLCC

DSTi

DSTo

F0o

B17

B16

B15

B14

B13

B12

B11

B10

B17

B16

B15

B14

B13

B12

B11

B10

B17

Channel Time 0

DSTi

DSTo

F0o

B17 B16 B15 B14 B13 B12 B11 B10

B17

Channel Time 0

B17 B16 B15 B14 B13 B12 B11 B10

B27 B26 B25 B24 B23 B22 B21 B20

Channel Time 16

MT8972BE Datasheet(PDF) 3 Page - Mitel Networks Corporation

MT8972BE Datasheet(HTML) 3 Page - Mitel Networks Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Download

Link URL