MT8971B/72B

9-108

Figure 2 - Pin Connections

Pin Description

Pin #

Name

Description

DIP PLCC

12

23

34

4,5,

6

5,7,

8

MS2-MS0 Mode Select inputs (Digital). The logic levels present on these pins select the various

operating modes for a particular application. See Table 1 for the operating modes.

7

9

RegC

Regulator Control output (Digital). A 512 kHz clock used for switch mode power

supplies. Unused in MAS/MOD mode and should be left open circuit.

810

F0/CLD

Frame Pulse/C-Channel Load (Digital). In DN mode a 244 ns wide negative pulse input

for the MASTER indicating the start of the active channel times of the device. Output for

the SLAVE indicating the start of the active channel times of the device. Output in MOD

mode providing a pulse indicating the start of the C-channel.

9

12

CDSTi/

CDi

Control/Data ST-BUS In/Control/Data In (Digital). A 2.048 Mbit/s serial control &

signalling input in DN mode. In MOD mode this is a continuous bit stream at the bit rate

selected.

10

13

CDSTo/

CDo

Control/Data ST-BUS Out/Control/Data Out (Digital). A 2.048 Mbit/s serial control &

signalling output in DN mode. In MOD mode this is a continuous bit stream at the bit rate

selected.

11

14

Negative Power Supply (0V).

12

15

DSTo/Do Data ST-BUS Out/Data Out (Digital). A 2.048 Mbit/s serial PCM/data output in DN mode.

In MOD mode this is a continuous bit stream at the bit rate selected.

13

16

DSTi/Di

Data ST-BUS In/Data In (Digital). A 2.048 Mbit/s serial PCM/data input in DN mode. In

MOD mode this is a continuous bit stream at the bit rate selected.

14

17

F0o/RCK Frame Pulse Out/Receive Bit Rate Clock output (Digital). In DN mode a 244 ns wide

negative pulse indicating the end of the active channel times of the device to allow daisy

chaining. In MOD mode provides the receive bit rate clock to the system.

15

19

C4/TCK

Data Clock/Transmit Baud Rate Clock (Digital). A 4.096 MHz TTL compatible clock

input for the MASTER and output for the SLAVE in DN mode. For MOD mode this pin

provides the transmit bit rate clock to the system.

16

21

OSC2

Oscillator Output. CMOS Output.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

22

21

20

19

18

17

16

15

22 PIN PDIP/CERDIP

LOUT

VBias

VRef

MS2

MS1

MS0

RegC

F0/CLD

CDSTi/CDi

CDSTo/CDo

VSS

VDD

LIN

TEST

LOUT DIS

Precan

OSC1

OSC2

C4/TCK

F0o/RCK

DSTi/Di

DSTo/Do

28 PIN PLCC

5

6

7

8

9

10

11

25

24

23

22

21

20

19

•

NC

LOUT DIS

Precan

OSC1

OSC2

NC

C4/TCK

MS2

NC

MS1

MS0

RegC

F0/CLD

NC