2-104

46-61

A0-A15

Address Bus. These inputs have three different functions. Inputs A0-A10 are used to

address internal memory locations during read or write operations in all modes except Shift

Register mode. In Shift Register mode, the levels latched in on A0-A10 program the delay

through the device. When the ME pin is tied high, the data latched in on A0-A15 is clocked

out on to the data bus (D0o-D15o).

62

CD

Change Detect. Open drain output which is pulled low when a change in the memory

contents from one frame to the next is detected by a Cyclic Redundancy Check (CRC).

Changes in memory contents resulting from microprocessor access do not cause CD to go

low. The output is reset to its normal high impedance state when the DS input is strobed,

while the device has been selected (CS is low).

63

Supply Voltage. +5V .

64

Ground.

65-68

D0o-D3o Output Data Bus. These three state outputs are part of a 16 bit data bus which is used to

clock out data from the device. Data is clocked out with the rising edge of the clock. See

Figures 24 to 26 for timing information. The bus is actively driven when ODE is tied high. It

is disabled when ODE is tied low. Tying CS high will also disable the output data bus in all

modes except Connect Memory and Shift Register Modes.

69

Ground.

70-73

D4o-D7o Output Data Bus. See description for pins 65-68.

74

Ground.

75-78

D8o-D11o Output Data Bus. See description for pins 65-68.

79

Ground.

80-83

D12o-D15

o

Output Data Bus. See description for pins 65-68.

84

Supply Voltage. +5V .

Pin Description

Pin #

Name

Description