MT9080AP datasheet(5/24 Pages) MITEL

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CMOS

MT9080

2-105

Functional Description

The SMX is a flexible memory module suitable for

use in the construction of timeslot interchange

circuits used in PCM voice or data switches.

The

device can be configured as a data memory or a

connection memory.

The SMX has separate 16 bit input and output data

busses.

bit

address

bus

and

full

microprocessor interface is also provided.

Data is clocked into and out of the device with the

signal applied at the CK (clock) input. Depending on

the mode of operation, the memory locations for the

read

write

operation

can

addressed

sequentially by the internal counter or randomly via

the external address bus.

A messaging sub-mode,

which permits the data latched in on the address bus

to be multiplexed on to the output data bus, is also

available (see ME pin description).

The SMX ensures integrity of the stored data by

performing a Cyclic Redundancy Check (CRC) on a

per frame basis.

When a

change in the memory

contents is detected from one frame to the next, the

Change Detect (CD) pin is pulled low.

The output

will be reset to its normal high impedance state when

DS input is strobed while CS is low (i.e., while the

device

has

been

selected

for

microprocessor

access). The CD output is not pulled low when the

memory contents have been modified by a processor

access to the device.

Modes Of Operation

The SMX can be programmed to operate in one of

eight modes as summarized in Table 1. The different

modes

are

used

realize

specific

switch

implementations. For example, to implement a 1024

channel switch, two SMXs are required.

One is

operated in Data Memory mode, while the second is

operated in Connect Memory mode. A 2048 channel

switch can be realized using three SMXs. Two of the

devices are operated, alternatively, in Counter and

External modes, the third serves as the Connection

Memory.

detailed

description

the

implementation is presented in the Applications

section of this data sheet. An outline of the device

functionality in each mode is presented below.

Table 1. SMX Modes of Operation

Mode

Name

Abbr.

Data Memory - 1

Data Memory - 2

Connect Memory - 1

Connect Memory - 2

Counter Mode

External Mode

Shift Register Mode

Data Memory - 3

DM-1

DM-2

CM-1

CM-2

CNT

EXT

DM-3

Data Memory Mode-1

Data Memory Mode-1 is designed for use in the

construction of a 1024 Channel Switch Matrix. Data

on the D0-D15 input bus is clocked into the SMX and

stored in memory locations addressed by the internal

11 bit counter. Data is clocked out according to the

addresses asserted on the address bus.

The pin

configuration of the device in this mode is illustrated

in Fig .3

Fig. 3 - Data Memory Modes 1 and 2 Pinout

The timing for the read and write operation is

illustrated in Fig. 4. The first half of each clock period

is used for precharging the internal bus.

Data is

latched in and out of the device with rising edge of

the CK clock. Correct operation of the device in this

mode requires 2048 clock cycles in a single frame

defined by the frame pulse.

Consequently, for

switching of 64 kbit/s PCM voice channels, the clock

frequency must be 16.384 Mbit/s with a frame rate of

8 kHz.

The address supplied on the address bus is latched

in with the first positive clock edge in a channel

timeslot. The contents of the memory location

addressed will be clocked out on D0-D15o with the

first positive clock edge in the next timeslot (see Fig.

4).

In Data Memory Mode-1, the delay through the

switch depends on the number of channel timeslots

between the input channel and the output channel. If

the time difference between the input channel and

output channel is less than two channels, data

clocked into the device in the current frame will be

clocked out in the next frame.

If the difference is

greater than or equal to two channels, data will be

clocked out in the same frame.

This concept is

further illustrated in Fig. 5.

Data

Input

Data

Output

D0i-D15i

A0-A15

ODE

D0o-D15o

DTA

MODE

From Control Interface

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