MT9300AL datasheet(9/29 Pages) MITEL

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Advance Information

MT9300

Serial Data Interface Timing

The MT9300 provides ST-BUS and GCI interface

timing. The Serial Interface clock frequency, C4i, is

4.096 MHz. The input and output data rate of the ST-

Bus and GCI bus is 2.048 Mb/s.

The 8 KHz input frame pulse can be in either ST-BUS

or GCI format. The MT9300 automatically detects

the presence of an input frame pulse and identiﬁes it

as either ST-BUS or GCI. In ST-BUS format, every

second falling edge of the C4i clock marks a bit

boundary, and the data is clocked in on the rising

edge of C4i, three quarters of the way into the bit cell

(See Figure 9). In GCI format, every second falling

edge of the C4i clock marks the bit boundary, and

data is clocked in on the second falling edge of C4i,

half the way into the bit cell (see Figure 10).

Memory Mapped Control and Status

registers

Internal memory and registers are memory mapped

into the address space of the HOST interface. The

internal

dual

ported

memory

mapped

into

segments on a “per channel” basis to monitor and

control

each

individual

echo

canceller

and

associated PCM channels. For example, in Normal

conﬁguration, echo canceller #5 makes use of

Echo Canceller B from group 2. It occupies the

internal address space from 0A0h to 0BFh and

interfaces to PCM channel #5 on all serial PCM I/O

streams.

Figure 7 - Memory Mapping of per channel

Control and Status Registers

As illustrated in Figure 7, the “per channel” registers

provide independent control and status bits for each

echo canceller. Figure 8 shows the memory map of

the

control/status

blocks

for

all

echo

cancellers.

00h Control Reg A1

01h

Decay Step Size Reg

02h

03h

Base

04h

06h

Reserved

Flat Delay Reg

Control Reg 2

Status Reg

Reserved

05h

Reserved

08h

Decay Step Number

07h

Reserved

0Ah

Rin Peak Detect Reg

0Ch

Sin Peak Detect Reg

0Eh

Error Peak Detect Reg

10h

Reserved

12h

DTDT Reg

14h

Reserved

16h

NLPTHR

18h

Step Size, MU

1Ah

Reserved

1Ch

Reserved

1Eh

Addr + Echo Canceller A

20h Control Reg B1

21h

Decay Step Size Reg

22h

23h

24h

26h

Reserved

Flat Delay Reg

Control Reg 2

Status Reg

Reserved

25h

Reserved

28h

Decay Step Number

27h

Reserved

2Ah

Rin Peak Detect Reg

2Ch

Sin Peak Detect Reg

2Eh

Error Peak Detect Reg

30h

Reserved

32h

DTDT Reg

34h

Reserved

36h

NLPTHR

38h

Step Size, MU

3Ah

Reserved

3Ch

Reserved

3Eh

Base

Addr + Echo Canceller B

Figure 6 - ST-BUS and GCI Interface Channel Assignment for 2Mb/s Data Streams

F0i

Rin/Sin

Rout/Sout

Channel 31

Channel 0

125

µsec

Channel 1

Channel 30

ST-Bus

F0i

GCI interface

Note: Refer to Figures 9 and 10 for timing details

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