MT9300AL datasheet(13/29 Pages) MITEL

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Advance Information

MT9300

Registers Description

Bit

Name

Description

Reset

When high, the power-up initialization is executed which presets all register bits

including this bit and clears the Adaptive Filter coefﬁcients.

INJDis

When high, the noise injection process is disabled. When low noise injection is

enabled.

BBM

When high the Back to Back conﬁguration is enabled.

When low the Normal conﬁguration is enabled.

Note: Do not enable Extended-Delay and BBM conﬁgurations at the same time.

Always set both BBM bits of the two echo cancellers (Control Register A1 and Control

PAD

When high, 12dB of attenuation is inserted into the Rin to Rout path.

When low the Rin to Rout path gain is 0dB.

Bypass

When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout. The

Adaptive Filter coefﬁcients are set to zero and the ﬁlter adaptation is stopped.

When low, output data on both Sout and Rout is a function of the echo canceller

algorithm.

AdpDis

When high, echo canceller adaptation is disabled. The MT9300 cancels echo.

When low, the echo canceller dynamically adapts to the echo path characteristics.

0 or 1

Bits marked as “1” or “0” are reserved bits and should be written as indicated.

ExtDl

When high, Echo Cancellers A and B of the same group are internally cascaded into

one 128ms echo canceller.

When low, Echo Cancellers A and B of the same group operate independently.

Note: Do not enable both Extended-Delay and BBM conﬁgurations at the same time.

Control Register B1 bit-0 is a reserved bit and should be written “0”.

Echo Canceller A, Control Register A1

Read/Write Address: 00H + Base Address

AdpDis

Bypass

PAD

BBM

INJDis

Reset

76543210

ExtDl

Echo Canceller B, Control Register B1

Read/Write Address: 20H + Base Address

AdpDis

Bypass

PAD

BBM

INJDis

Reset

76543210

Reset Value:

00H.

Reset Value:

02H.

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