MT9300AL datasheet(4/29 Pages) MITEL

4 / 29 page

MT9300

Advance Information

140

MCLK

Master Clock (Input). Nominal 10MHz or 20MHz Master Clock input. May be

connected to an asynchronous (relative to frame signal) clock source.

143

Fsel

Frequency select (Input). This input selects the Master Clock frequency

operation. When Fsel pin is low, nominal 19.2MHz Master Clock input must be

applied. When Fsel pin is high, nominal 9.6MHz Master Clock input must be

applied.

146

PLLVSS

PLL Ground. Must be connected to VSS

147

PLLVDD

PLL Power Supply. Must be connected to VDD

152

TMS

Test Mode Select (3.3V Input). JTAG signal that controls the state transitions of

the TAP controller. This pin is pulled high by an internal pull-up when not driven.

153

TDI

Test Serial Data In (3.3V Input). JTAG serial test instructions and data are shifted

in on this pin. This pin is pulled high by an internal pull-up when not driven.

154

TDO

Test Serial Data Out (Output). JTAG serial data is output on this pin on the falling

edge of TCK. This pin is held in high impedance state when JTAG scan is not

enabled.

155

TCK

Test Clock (3.3V Input). Provides the clock to the JTAG test logic.

156

TRST

Test Reset (3.3V Input). Asynchronously initializes the JTAG TAP controller by

putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-up

or held low, to ensure that the MT9300 is in the normal functional mode. This pin is

pulled by an internal pull-down when not driven.

158

RESET

Device Reset (Schmitt Trigger Input). An active low resets the device and puts

the MT9300 into a low-power stand-by mode.

When the RESET pin is returned to logic high and a clock is applied to the

MCLK pin, the device will automatically execute initialization routines, which

preset all the Control and Status Registers to their default power-up values.

Pin Description (continued)

Pin #

Name

Description

Device Overview

The

MT9300

architecture

contains

echo

cancellers divided into 16 groups. Each group has

two echo cancellers, Echo Canceller A and Echo

Canceller B. Each group can be conﬁgured in

Normal,

Extended

Delay

Back-to-Back

conﬁgurations. In Normal conﬁguration, a group of

echo cancellers provides two channels of 64ms echo

cancellation, which run independently on different

channels. In Extended Delay conﬁguration, a group

echo

cancellers

achieves

128ms

echo

cancellation by cascading the two echo cancellers (A

& B). In Back-to-Back conﬁguration, the two echo

cancellers from the same group are positioned to

cancel echo coming from both directions in a single

channel,

providing

full-duplex

64ms

echo

cancellation.

Each echo canceller contains the following main

elements (see Figure 3).

•

Adaptive Filter for estimating the echo channel

•

Subtractor for cancelling the echo

•

Double-Talk detector for disabling the ﬁlter

adaptation during periods of double-talk

•

Non-Linear Processor for suppression of

residual echo

•

Disable Tone Detectors for detecting valid

disable tones at the input of receive and send

paths

•

Narrow-Band Detector for preventing Adaptive

Filter divergence caused by narrow-band

signals

•

Offset Null ﬁlters for removing the DC

component in PCM channels

•

12dB attenuator for signal attenuation

•

Parallel controller interface compatible with

Motorola microcontrollers

•

PCM encoder/decoder compatible with

µ/A-

Law ITU-T G.711 or Sign-Magnitude coding

MT9300AL Datasheet(PDF) 4 Page - Mitel Networks Corporation

MT9300AL Datasheet(HTML) 4 Page - Mitel Networks Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Datasheet Download

Link URL