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SM5865AM Datasheet(PDF) 11 Page - Nippon Precision Circuits Inc |
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SM5865AM Datasheet(HTML) 11 Page - Nippon Precision Circuits Inc |
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11 / 17 page ![]() SM5865AM NIPPON PRECISION CIRCUITS—11 System Clock Divider (CKDVN) The SM5865AM has a built-in divide-by-2 system clock frequency divider. The divider enables the internal system clock to operate at half the input fre- quency, for example when the external master clock input frequency is high. System Reset (RSTN) The device should be reset in the following cases. s At power ON s When the system clock CKI stops, or other abnor- malities occur. The device is reset by applying a LOW-level pulse on RSTN. Audio Data Input (DI, BCKI, WCKI, IWSL) Input data format The audio data is input in MSB-first, 2s-comple- ment, 24-bit/20-bit serial format. The input word bit length is selected by IWSL, 24-bit when HIGH or open circuit, and 20-bit when LOW. Jitter-free function Serial input data bits on DI are read into an SIPO register (serial-to-parallel converter register) on the rising edge of the bit clock BCKI where the serial data is converted into parallel data. The internal par- allel data control timing is derived from the system clock, and is not affected by any jitter on the input data clocks (WCKI and BCKI). After a reset opera- tion is released when RSTN goes HIGH, the internal timing and the WCKI input timing are phase com- pared on the first and subsequent WCKI falling edges and the comparison result is used to perform timing adjustment to maintain the word boundary relationship between the internal timing and the WCKI clock. 88.2 kHz 11.2896 MHz (128fs) 16fs 2 4 88.2 kHz 16.9344 MHz (192fs) 24fs 3 6 88.2 kHz 22.5792 MHz (256fs) 32fs 4 8 88.2 kHz 33.8688 MHz (384fs) 48fs 6 12 96 kHz 12.288 MHz (128fs) 16fs 2 4 96 kHz 18.432 MHz (192fs) 24fs 3 6 96 kHz 24.576 MHz (256fs) 32fs 4 8 96 kHz 36.864 MHz (384fs) 48fs 6 12 192 kHz 24.576 MHz (128fs) 16fs 2 4 192 kHz 36.864 MHz (192fs) 24fs 3 6 1. When CKDVN = LOW, the system clock frequency fCKI is halved, so the values shown are half the input frequency required for the same sampling rate and internal factors. Table 2. System clock frequencies (CKDVN = HIGH) fs System clock frequency1 fCKI Noise shaper operating rate Internal factor (8fs input) Internal factor (4fs input) |
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