TMP75C

SBOS707B – APRIL 2014 – REVISED AUGUST 2014

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7.3.3.7 Two-Wire Timing

The TMP75C is two-wire and SMBus compatible. Figure 8 to Figure 10 describe the various operations on the

TMP75C. Parameters for Figure 8 are defined in Table 3. Bus definitions are:

Bus Idle

Both SDA and SCL lines remain high.

Start Data Transfer A change in the state of the SDA line, from high to low, while the SCL line is high defines a

start condition. Each data transfer is initiated with a start condition.

Stop Data Transfer A change in the state of the SDA line from low to high while the SCL line is high defines a

stop condition. Each data transfer is terminated with a repeated start or stop condition.

Data Transfer The number of data bytes transferred between a start and a stop condition is not limited, and is

determined by the master device.

The receiver acknowledges the transfer of data. It is also possible to use the TMP75B for

single-byte updates. To update only the MS byte, terminate communication by issuing a start

or stop condition on the bus.

Acknowledge Each receiving device, when addressed, must generate an acknowledge bit.

A device that acknowledges must pull down the SDA line during the acknowledge clock

pulse so that the SDA line is stable low during the high period of the acknowledge clock

pulse. Setup and hold times must be taken into account. When a master receives data, the

termination of the data transfer can be signaled by the master generating a not-acknowledge

(1) on the last byte transmitted by the slave.

Table 3. Timing Diagram Requirements

FAST MODE

HIGH-SPEED MODE

SYMBOL

PARAMETER

MIN

MAX

MIN

MAX

UNIT

0.001

0.4

0.001

3

MHz

SCL operating frequency

0.001

0.4

0.001

2.5

MHz

1300

160

ns

Bus free time between

stop and start conditions

1300

260

ns

Hold time after repeated start condition.

600

160

ns

After this period, the first clock is generated.

Repeated start condition setup time

600

160

ns

Stop condition setup time

600

160

ns

0

900

0

100

ns

Data hold time

0

900

0

140

ns

100

10

ns

Data setup time

100

20

ns

1300

190

ns

SCL clock low period

1300

240

ns

SCL clock high period

600

60

ns

Data rise and fall time

300

80

ns

Clock rise and fall time

300

40

ns

Clock and data rise time for SCLK

≤ 100 kHz

1000

ns

12

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