SM8213 datasheet(16/33 Pages) NPC

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SM8213AM

NIPPON PRECISION CIRCUITS—16

Received Data Transmission (SM8213AM to CPU)

In lock mode, if the receive data for the frame is rec-

ognized as one of the 28 normal addresses or a

dummy address with 2 bit errors or less, then the data

is temporarily stored in the transmit buffer and then

error correction and other processing takes place.

After processing, ATTN goes LOW to inform the

CPU that transmit ready data is available.

The SM8213AM switches the data internally and

then outputs 32-bit data, shown in table 7, on SDO in

sync with the falling edge of the SCK clock. The

CPU can then read the data on either the SCK rising

edge or the falling edge.

The message bits (1 to 20), which are the 13th to

32nd bits of the detected address data, comprises 18

address information bits and 2 function bits.

When the 32-bit transmission ends, ATTN goes

HIGH to indicate that all necessary information has

been transmitted.

When an address is detected, the next 32-bit data

code word is received. The BCH(31,21) format error

check bits are checked and if a 1-bit or two consecu-

tive bit errors occur, they are corrected. Two random

bit errors, or three or more bit errors are not cor-

rected.

If the corrected data MSB is 1, the data is recognized

as a message, data reception continues and the cor-

rected message data and error check ﬂags are sent to

the CPU as 32-bit data, shown in table 7, with the

same data handling as an address. In this case also,

ATTN goes LOW after processing to inform the

CPU that transmit ready data is available. The time

from when ATTN goes LOW until the CPU sends the

SCK should be the same as shown in ﬁgure 9. Also,

when the message continues, the normal SCK clock

speed becomes faster than the receive signal bit rate

and as a result there is a limit to the transmitted

information capacity. As ATTN is used as the trans-

mit ready data available signal output, it can be used

as the CPU interrupt signal to receive data with the

timing shown in ﬁgure 9.

Conversely, when the decoder takes ATTN LOW to

indicate transmit ready data is available, the micro-

controller operates under normal starting conditions

(high-speed clock operation), and 32-bit clock is

input on SCK. After data is read in and until ATTN

goes LOW for the next transmit ready data signal,

the series processing should be such that it takes less

than {32

× (bit rate)} time. If it takes longer than this

amount of time, the succeeding data may not be out-

put correctly.

When the MSB is 0 and data is recognized as an idle

signal or idle code, data reception and data transfer

to the CPU stops after the end-of-message is output

for addresses not matching the self address.

However, when CPU BREAK input interrupt end-of-

message method is selected (see “Flag Setting” sec-

tion), data is treated as a message and reception con-

tinues even if the MSB is 0.

When sending data from the decoder to the micro-

controller, the SCK clock frequency should not be

less than 512, (1200), [2400] Hz. If this occurs, the

SCK counter is reinitialized. This function, however,

does make restoring operation easy even if this or

another clock is accidentally input.

Figure 9. Received data transmit timing

ATTN

SCK

SDO

DATA

8-bit

× 4-byte = 32-bit unit time clock

8-bit

× 4-byte = 32-bit unit time data

Refer to the AC Characteristics section for detailed timing specifications.

0ms min

32 bit time

0ms min

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