AS1138 datasheet(27/30 Pages) ETC2

27 / 30 page

AS1138

Akros Silicon, Inc.

6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA

408.746.9000

www.AkrosSilicon.com

THERMAL

DE-RATING

AND

BOARD

LAYOUT CONSIDERATIONS

The AS1138 is capable of operating to an industrial

temperature range of 85 ºC in ambient air, without forced

cooling. A thermal pad on the underside of the package

dissipates the heat generated by the PD die.

In 30W applications, designers must consider thermal

dissipation as an integral part of their system architecture

and plan to remove heat via this pad.

If the PCB landing pattern is properly designed, the QFN

package

should

exhibit

thermal

resistance

ΘJA

=31°C/W. For adequate heat dissipation, the board

layout must include a ground pad which provides both the

ground

connection

and

dissipates

the

heat

energy

produced in the chip. Thermal vias are used to draw heat

away from the PD package and to transfer it to the

backside of the system PCB.

The recommended PCB layout for the AS1138 is shown in

Figure 33 below:

Figure 33 - AS1138 PCB Footprint (Top View)

Thermal Vias

0.31 mm dia.

1.27 mm pitch

9 places

3.80 mm

0.65 mm

0.4

0.5 mm

0.3 mm

Pin 1

Pin 20

AS1138 Datasheet(PDF) 27 Page - List of Unclassifed Manufacturers

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