HD3SS3220RNHT datasheet(29/43 Pages) TI1

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HD3SS3220

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SLLSES1 – DECEMBER 2015

8.2.4.1 Design Requirements

For this design example, use the parameters shown in Table 14.

Table 14. Design Parameters, UFP Port

PARAMETER

EXAMPLE

COMMENTS

VDD5

5 V

VBUS from Type-C port can be used.

1.8 V is also an option.

I2C I/O Supply

3.3 V

When using the 3.3-V supply, the customer must ensure that the VDD is 3 V

and above. Otherwise the I2C may back power the device

VCC33

3.3 V

3-3.6 V range allowed.

75-200 nF range allowed.

For TX pairs only, RX pairs will be biased by host Receiver. Note that

AC Coupling Capacitors for SS signals

100 nF

HD3SS3220 requires a common mode biasing of 0-2 V. If host receiver has

bias voltage outside this range, appropriate additional ac coupling caps and

biasing of HD3SS3220 RX pairs needed.

Smaller values can be used, but leakage needs to be considered for device

Pull-up Resistors: DIR, INT_N

200 K

power budget calculations.

Pull-up Resistors: I2C

4.7 K

Series resistor: VBUS_DET

900 K

8.2.4.2 Detailed Design Procedure

HD3SS3220 can be used to design a USB Type-C DFP Port. An example schematic for UFP implementation is

illustrated in Figure 12.

9 Power Supply Recommendations

HD3SS3220 has 4.5 to 5.5-V supply voltage requirement. The device can be powered from the same rail that

provides power for V(BUS).

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