HD3SS3220RNHT datasheet(4/43 Pages) TI1

4 / 43 page

HD3SS3220

SLLSES1 – DECEMBER 2015

www.ti.com

Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

TX1n

I/O

Type-C Port - USB SuperSpeed differential Signal TX1 negative

TX1p

I/O

Type-C Port - USB SuperSpeed differential Signal TX1 positive

RX2n

I/O

Type-C Port - USB SuperSpeed differential Signal RX2 negative

RX2p

I/O

Type-C Port - USB SuperSpeed differential Signal RX2 positive

TX2n

I/O

Type-C Port - USB SuperSpeed differential Signal TX2 negative

TX2p

I/O

Type-C Port - USB SuperSpeed differential Signal TX2 positive

Tri-level input pin to indicate I2C address or GPIO mode:

H (connect to VDD5) - I2C is enabled and I2C 7-bit address is 0x67.

ADDR

NC - GPIO mode (I2C is disabled)

L (connect to GND) - I2C is enabled and I2C 7-bit address is 0x47.

ADDR pin should be pulled up to VDD if high configuration is desired

The INT_N/OUT3 is a dual-function pin.

When used as the INT_N, the pin is an open drain output in I2C control mode and is an

active low interrupt signal for indicating changes in I2C registers.

INT_N/OUT3

When used as OUT3, the pin is in audio accessory detect in GPIO mode:

H - no detection, and

L - audio accessory connection detected.

VCONN_FAU

Open drain output. Asserted low when VCONN overcurrent detected.

LT_N

The SDA/OUT1 is a dual-function pin.

When I2C is enabled (ADDR pin is high or low), this pin is the I2C communication data

signal.

SDA/OUT1

I/O

When in GPIO mode (ADDR pin is NC), this pin is an open drain output for communicating

Type-C current mode detect when the device is in UFP mode:

H – Default (900 mA) current mode detected, and

L – Medium (1.5 A) or High (3 A) Current Mode detected.

The SCL/OUT2 is a dual function pin.

When I2C is enabled (ADDR pin is high or low), this pin is the I2C communication clock

signal.

SCL/OUT2

I/O

When in GPIO mode (ADDR pin is NC), this pin is an open drain output for communicating

Type-C current mode detect when the device is in UFP mode:

H – Default or Medium current mode detected, and

L – High current mode detected.

Open drain output. Asserted low when CC pin detected device attachment when port is a

source (DFP), or dual-role (DRP) acting as source (DFP).

ENn_CC

Enable signal for CC controller. Enable is active low.

VDD5

5-V Power supply

The thermal PAD must be connected to GND, see the Thermal Pad connection techniques

Thermal Pad

–

(SLMA002).

Submit Documentation Feedback

Product Folder Links: HD3SS3220

HD3SS3220RNHT Datasheet(PDF) 4 Page - Texas Instruments

HD3SS3220RNHT Datasheet(HTML) 4 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

Datasheet Download

Link URL