HD3SS3220RNHT datasheet(8/43 Pages) TI1

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50%

SEL

90%

VOUT

50%

tSW_ON

tSW_OFF

10%

DIR

Axp

Axn

Bxp/Cxp

Bxn/Cxn

RSC = 50

VCC

RL = 50

HD3SS3220

SLLSES1 – DECEMBER 2015

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6.6 Timing Requirements

MIN

NOM

MAX

UNIT

I2C (SDA, SCL)

tSU:DAT

Data setup time

250

tSU;STA

Set-up time, SCL to start condition

4.7

µs

tHD,STA

Hold time,(repeated) start condition to SCL

0.4

µs

tSU:STO

Set up time for STOP condition

0.4

µs

tBUF

Bus free time between a STOP and START condition

4.7

µs

fSCL

SCL clock frequency; I2C mode for local I2C control

100

Rise time of both SDA and SCL signals

1000

Fall time of both SDA and SCL signals

300

SS MUX

tPD

Switch propagation delay See Figure 3

tSW_ON

Switching time DIR-to-Switch ON See Figure 2

0.5

µs

tSW_OFF

Switching time DIR-to-Switch OFF See Figure 2

0.5

µs

tSK_INTRA

Intra-pair output skew See Figure 3

tSK_INTER

Inter-pair output skew See Figure 3

Figure 1. Test Setup

Figure 2. Switch On and Off Timing Diagram

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