MSP430F5259_15 datasheet(4/112 Pages) TI1

4 / 112 page

MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256

MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252

SLAS903B – MAY 2013 – REVISED NOVEMBER 2015

www.ti.com

Table of Contents

5.20

Typical Characteristics – Outputs, Full Drive

Device Overview

......................................... 1

Strength (PxDS.y = 1)

............................... 25

1.1

Features

.............................................. 1

5.21

Crystal Oscillator, XT1, Low-Frequency Mode

..... 26

1.2

Applications

........................................... 2

5.22

Crystal Oscillator, XT2

.............................. 27

1.3

Description

............................................ 2

5.23

Internal Very-Low-Power Low-Frequency Oscillator

1.4

Functional Block Diagram

............................ 3

(VLO)

................................................ 28

Revision History

......................................... 5

5.24

Internal Reference, Low-Frequency Oscillator

Device Comparison

..................................... 6

(REFO)

.............................................. 28

Terminal Configuration and Functions

.............. 7

5.25

DCO Frequency

..................................... 29

4.1

Pin Diagrams

......................................... 7

5.26

PMM, BOR

.......................................... 30

4.2

Signal Descriptions

................................... 9

5.27

PMM, Core Voltage

................................. 30

Specifications

........................................... 14

5.28

PMM, SVS High Side

............................... 31

5.1

Absolute Maximum Ratings

........................ 14

5.29

PMM, SVM High Side

............................... 32

5.2

ESD Ratings

........................................ 14

5.30

PMM, SVS Low Side

................................ 32

5.3

Recommended Operating Conditions

............... 14

5.31

PMM, SVM Low Side

............................... 33

5.4

Active Mode Supply Current Into VCC Excluding

5.32

Wake-Up Times From Low-Power Modes and

External Current

..................................... 17

Reset

................................................ 33

5.5

Low-Power Mode Supply Currents (Into VCC)

5.33

Timer_A

............................................. 34

Excluding External Current

.......................... 18

5.34

Timer_B

............................................. 34

5.6

Thermal Characteristics

............................ 19

5.35

USCI (UART Mode) Clock Frequency

.............. 35

5.7

Schmitt-Trigger Inputs – General-Purpose I/O

5.36

USCI (UART Mode)

................................. 35

DVCC Domain

(P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RSTDVCC)

.... 20

5.37

USCI (SPI Master Mode) Clock Frequency

......... 35

5.8

Schmitt-Trigger Inputs – General-Purpose I/O DVIO

5.38

USCI (SPI Master Mode)

............................ 35

Domain

5.39

USCI (SPI Slave Mode)

............................. 37

(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0

5.40

USCI (I2C Mode)

.................................... 39

to P7.5, RST/NMI, BSLEN)

................................ 20

5.41

10-Bit ADC, Power Supply and Input Range

5.9

Inputs – Interrupts DVCC Domain Port P6

Conditions

........................................... 40

(P6.0 to P6.7)

.............................................. 20

5.42

10-Bit ADC, Timing Parameters

.................... 40

5.10

Inputs – Interrupts DVIO Domain Ports P1 and P2

(P1.0 to P1.7, P2.0 to P2.7)

................................ 20

5.43

10-Bit ADC, Linearity Parameters

................... 41

5.11

Leakage Current – General-Purpose I/O DVCC

5.44

REF, External Reference

........................... 41

Domain

5.45

REF, Built-In Reference

............................. 42

(P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)

................. 21

5.46

Comparator_B

....................................... 43

5.12

Leakage Current – General-Purpose I/O DVIO Domain

(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0

5.47

Flash Memory

....................................... 44

to P7.5)

..................................................... 21

5.48

JTAG and Spy-Bi-Wire Interface

.................... 44

5.13

Outputs – General-Purpose I/O DVCC Domain (Full

5.49

DVIO BSL Entry

..................................... 45

Drive Strength)

Detailed Description

................................... 46

(P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)

................. 21

6.1

CPU (Link to user's guide)

......................... 46

5.14

Outputs – General-Purpose I/O DVCC Domain

(Reduced Drive Strength)

6.2

Operating Modes

.................................... 47

(P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)

................. 22

6.3

Interrupt Vector Addresses

.......................... 48

5.15

Outputs – General-Purpose I/O DVIO Domain (Full

6.4

Memory Organization

............................... 49

Drive Strength)

6.5

Bootloader (BSL)

.................................... 50

(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0

to P7.5)

..................................................... 22

6.6

JTAG Operation

..................................... 52

5.16

Outputs – General-Purpose I/O DVIO Domain

6.7

Flash Memory (Link to user's guide)

............... 54

(Reduced Drive Strength)

6.8

RAM (Link to user's guide)

......................... 54

(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0

6.9

Peripherals

.......................................... 55

to P7.5)

..................................................... 22

5.17

Output Frequency – General-Purpose I/O DVCC

6.10

Input/Output Schematics

............................ 77

Domain

6.11

Device Descriptors

.................................. 93

(P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)

................. 23

Device and Documentation Support

............... 95

5.18

Output Frequency – General-Purpose I/O DVIO

7.1

Device Support

...................................... 95

Domain

(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0

7.2

Documentation Support

............................. 98

to P7.5)

..................................................... 23

7.3

MSP430F5259 Datasheet(PDF) 4 Page - Texas Instruments

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