TLE6244 datasheet(31/70 Pages) INFINEON

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Final Data Sheet

V4.2, 2003-08-29

TLE 6244X

When the bit BMUX in CONFIG is set to Low, the power stages 1...7 and 9...16 are controlled by

the µsec-bus-interface on condition that registers MUX_REG1/2 are configured for serial access.

The received µsec-bus bit stream (D0... D15) is latched into a 16-bit register by the rising edge at

SSY. Power stages 1...7 and 9...16 are switched according to bits D0...D7 and D9...D15:

Bit Dx = 0:

Power stage OUTx is switched on

Bit Dx = 1:

Power stage OUTx is switched off

State of reset:

FFFFH

Because the power stage 8 is not controlled by the µsec-bus-interface, the corresponding bit D8

can be used as test bit, that can be read back by the SPI-interface (see register RD_INP1).

If the µsec-bus-interface is used to control the power stages, the input pins IN1..IN5 and

IN8...IN15 can be used as input port expander by reading the status of the input pins by the SPI-

commands RD_INP1/2.

µsec-bus

control of

power stage

µsec-bus

control of

power stage

OUT14

µsec-bus Test

Bit

OUT1

OUT11

OUT2

D10

OUT10

OUT3

D11

OUT9

OUT4

D12

OUT12

OUT5

D13

OUT13

OUT6

D14

OUT16

OUT7

D15

OUT15

TLE6244 Datasheet(PDF) 31 Page - Infineon Technologies AG

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