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S3P72P9 Datasheet(PDF) 71 Page - Samsung semiconductor |
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S3P72P9 Datasheet(HTML) 71 Page - Samsung semiconductor |
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71 / 225 page ![]() S3C72P9/P72P9 (Preliminary Spec) MEMORY MAP 4-21 IPR — Interrupt Priority Register CPU FB2H Bit 3 2 1 0 Identifier IME .2 .1 .0 RESET RESET Value 0 0 0 0 Read/Write W W W W Bit Addressing 1/4 4 4 4 IME Interrupt Master Enable Bit 0 Disable all interrupt processing 1 Enable processing for all interrupt service requests IPR.2 – .0 Interrupt Priority Assignment Bits 0 0 0 Process all interrupt requests at low priority 0 0 1 Only INTB and INT4 interrupts are at high priority 0 1 0 Only INT0 interrupt is at high priority 0 1 1 Only INT1 interrupt is at high priority 1 0 0 Only INTS interrupt is at high priority 1 0 1 Only INTT0 interrupt is at high priority 1 1 0 Only INTT1 interrupt is at high priority 1 1 1 Only INTK interrupt is at high priority |
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