ADG5243F datasheet(26/30 Pages) AD

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ADG5243F

Data Sheet

Rev. 0 | Page 26 of 30

THEORY OF OPERATION

SWITCH ARCHITECTURE

Each channel of the ADG5243F consists of a parallel pair of

N-channel diffused metal-oxide semiconductor (NDMOS) and

P-channel DMOS (PDMOS) transistors. This construction

provides excellent performance across the signal range. The

ADG5243F channels operate as standard switches when input

signals with a voltage between POSFV and NEGFV are applied.

For example, the on resistance is 250 Ω typically and opening or

closing the switch is controlled using the appropriate control pins.

Additional internal circuitry enables the switch to detect

overvoltage inputs by comparing the voltage on a source pin

with POSFV and NEGFV. A signal is considered overvoltage if

it exceeds these secondary supply voltages by the voltage threshold,

VT. The threshold voltage is typically 0.7 V, but can range from

0.8 V at −40°C down to 0.6 V at +125°C. See Figure 26 to see the

change in VT with operating temperature.

The maximum voltage that can be applied to any source input is

+55 V or −55 V. When the device is powered using a single supply

of 25 V or greater, the maximum negative signal level is reduced. It

reduces from −55 V at VDD = +25 V to −40 V at VDD = +40 V to

remain within the 80 V maximum rating. Construction of the

process allows the channel to withstand 80 V across the switch

when it is opened. These overvoltage limits apply whether the

power supplies are present or not.

ESD

PROTECTION

INx

POSFV

NEGFV

ESD

FAULT

DETECTOR

LOGIC

BLOCK

SWITCH

DRIVER

Figure 48. Switch Channel and Control Function

When an overvoltage condition is detected on a source pin (Sx),

the switch automatically opens regardless of the digital logic

state and the source pin becomes high impedance. If a source

pin is selected that is in fault, the drain pin is pulled to the

supply that was exceeded. For example, if the source voltage

exceeds POSFV, the drain output pulls to POSFV. If the source

voltage exceeds NEGFV, the drain output pulls to NEGFV. In

Figure 27, the voltage on the drain pin can be seen to follow the

voltage on the source pin until the switch turns off completely.

The drain pin then pulls to GND due to the 1 kΩ load resistor;

otherwise, it pulls to the POSFV supply. The maximum voltage

on the drain is limited by the internal ESD diodes and the rate

at which the output voltage discharges is dependent on the load

at the pin.

During overvoltage conditions, the leakage current into and out

of the source pins is limited to tens of microamperes. If the source

pin is unselected, only nanoamperes of leakage appear on the

drain pin. However, if the source is selected, the pin is pulled to

the supply rail. The device that pulls the drain pin to the rail has

an impedance of approximately 40 kΩ; thus, the Dx pin current

is limited to approximately 1 mA during a shorted load condition.

This internal impedance also determines the minimum external

load resistance required to ensure that the drain pin is pulled to

the desired voltage level during a fault.

When an overvoltage event occurs, the channels undisturbed by

the overvoltage input continue to operate normally without

additional crosstalk.

ESD Performance

The drain pins have ESD protection diodes to the secondary

supply rails and the voltage at these pins must not exceed the

secondary supply voltages, POSFV and NEGFV. The source

pins have specialized ESD protection that allows the signal voltage

to reach ±55 V regardless of supply voltage level. Exceeding

±55 V on any source input may damage the ESD protection

circuitry on the device. See Figure 48 for an overview of the

switch channel.

Trench Isolation

In the ADG5243F, an insulating oxide layer (trench) is placed

between the NDMOS and the PDMOS transistors of each switch.

Parasitic junctions, which occur between the transistors in

junction-isolated switches, are eliminated, and the result is a

switch that is latch-up immune under all circumstances. The

device passes a JESD78D latch-up test of ±500 mA for 1 sec,

which is the harshest test in the specification.

NDMOS

PDMOS

P-WELL

N-WELL

BURIED OXIDE LAYER

HANDLE WAFER

TRENCH

Figure 49. Trench Isolation

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