IS25LP032 datasheet(59/90 Pages) ISSI

59 / 90 page

IS25LP032/064/128

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

10/03/2014

8.30 SOFTWARE RESET (RESET-ENABLE (RSTEN, 66h) AND RESET (RST, 99h)) AND HARDWARE RESET

The Software Reset operation is used as a system reset that puts the device in normal operating mode. During

the Reset operation, the value of volatile registers will default back to the value in the corresponding non-volatile

requires the Reset-Enable command followed by the Reset command. Any command other than the Reset

command after the Reset-Enable command will disable the Reset-Enable.

Execute the CE# pin low  sends the Reset-Enable command (66h), and drives CE# high. Next, the host drives

CE# low again, sends the Reset command (99h), and pulls CE# high.

Only for the dedicated parts that have the RESET# pin, Hardware Reset function is available. The RESET# pin

will be solely applicable in SPI mode and when the QE bit is disabled. The RESET# pin has the highest priority

among all the input signals and will reset the device to its initial power-on state regardless of the state of all

other pins (CS, IOs, SCK and WP#).

In order to activate Hardware Reset, the RESET# pin must be driven low for a minimum period of t

RESET (1µs).

Drive RESET# low for a minimum period of t

RESET will interrupt any on-going internal and external operations,

release the device from deep power down mode

1, disable all input signals, force the output pin enter a state of

high impedance, and reset all the read parameters. If the RESET# pulse is driven for a period shorter than 1µs,

it may still reset the device, however the 1µs minimum period is recommended to ensure the reliable operation.

The required wait time after activating a HW Reset before the device will accept another instruction (tHWRST) is

the same as the maximum value of tSUS (100µs).

The Software/Hardware Reset during an active Program or Erase operation aborts the operation, which can

result in corrupting or losing the data of the targeted address range. Depending on the prior operation, the reset

timing may vary. Recovery from a Write operation will require more latency than recovery from other operations.

Note 1: The Status and Function Registers remain unaffected.

Figure 8.47 SOFTWARE RESET ENABLE, SOFTWARE RESET OPERATIONS (RSTEN, 66h + RST, 99h)

Instruction = 66h

CE#

SCK

SIO

Mode 3

Mode 0

Instruction = 99h

High Impedance

IS25LP032 Datasheet(PDF) 59 Page - Integrated Silicon Solution, Inc