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Data Sheet

AD9690

Table 15. DDC Samples, Chip Decimation Ratio = 16

Real (I) Output (Complex to Real Enabled)

Complex (I/Q) Outputs (Complex to Real Disabled)

HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 16)

Not applicable

N + 1

Not applicable

N + 2

Not applicable

N + 3

DCM = decimation.

If the chip decimation ratio is set to decimate by 4, DDC 0 is set to use HB2 + HB1 filters (complex outputs decimate by 4), and DDC 1 is

set to use HB4 + HB3 + HB2 + HB1 filters (real outputs decimate by 8), then DDC 1 repeats its output data two times for every one

DDC 0 output. The resulting output samples are shown in Table 16.

Table 16. DDC Output Samples when Chip DCM1 = 4, DDC 0 DCM1 = 4 (Complex), and DDC 1 DCM1 = 8 (Real)

DDC 0

DDC 1

DDC Input Samples

Output Port I

Output Port Q

Output Port I

Output Port Q

I0 [N]

Q0 [N]

I1 [N]

Not applicable

N + 1

N + 2

N + 3

N + 4

I0 [N + 1]

Q0 [N + 1]

I1 [N + 1]

Not applicable

N + 5

N + 6

N + 7

N + 8

I0 [N + 2]

Q0 [N + 2]

I1 [N]

Not applicable

N + 9

N + 10

N + 11

N + 12

I0 [N + 3]

Q0 [N + 3]

I1 [N + 1]

Not applicable

N + 13

N + 14

N + 15

DCM = decimation.

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