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AD9690 Datasheet(PDF) 69 Page - Analog Devices

Part # AD9690
Description  14-Bit, 1 GSPS/500 MSPS JESD204B, Analog-to-Digital Converter
PDF  77 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9690 Datasheet(HTML) 69 Page - Analog Devices

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Data Sheet
AD9690
Reg
Addr
(Hex)
Register
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Default
Notes
0x271
Signal
Monitor
Period
Register 0
Signal monitor period, Bits[7:0]
0x80
In deci-
mated
output
clock
cycles
0x272
Signal
Monitor
Period
Register 1
Signal monitor period, Bits[15:8]
0x00
In deci-
mated
output
clock
cycles
0x273
Signal
Monitor
Period
Register 2
Signal monitor period, Bits[23:16]
0x00
In deci-
mated
output
clock
cycles
0x274
Signal
monitor
result control
0
0
0
Result
update
1 = update
results (self
clear)
0
0
0
Result
selection
0 =
reserved
1 = peak
detector
0x01
0x275
Signal
Monitor
Result
Register 0
Signal monitor result, Bits[7:0]
When Register 0x0274[0] = 1, result bits [19:7] = peak detector absolute value [12:0]; result bits [6:0] = 0
Read
only
Updated
based on
Reg.
0x274[4]
0x276
Signal
Monitor
Result
Register 1
Signal monitor result, Bits[15:8]
Read
only
Updated
based on
Reg.
0x274[4]
0x277
Signal
Monitor
Result
Register 1
0
0
0
0
Signal monitor result, Bits[19:16]
Read
only
Updated
based on
Reg.
0x274[4]
0x278
Signal
monitor
period
counter
result
Period count result, Bits[7:0]
Read
only
Updated
based on
Reg.
0x274[4]
0x279
Signal
monitor
SPORT over
JESD204B
control
0
0
0
0
0
0
00 = reserved
11 = enable
0x00
0x27A
SPORT over
JESD204B
input
selection
0
0
0
0
0
0
Peak
detector
0 =
disabled
1 =
enabled
0
0x00
DDC Function Registers (See the Digital Downconverter (DDC) Section)
0x300
DDC synch
control
0
0
0
DDC NCO
soft reset
0 = normal
operation
1 = reset
0
0
Synchronization mode
(triggered by SYSREF±)
00 = disabled
01 = continuous
11 = 1-shot
Rev. 0 | Page 69 of 77



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