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Data Sheet

AD9690

Rev. 0 | Page 49 of 77

8-BIT/10-BIT

ENCODER

SERDOUT0±

SERDOUT1±

TAIL BITS

0x571[6]

SERIALIZER

ADC

SYMBOL0

SYMBOL1

A13

A12

A11

A10

MSB

LSB

CONTROL BITS

ADC TEST PATTERNS

(RE0x550,

REG 0x551 TO

REG 0x558)

JESD204B SAMPLE

CONSTRUCTION

JESD204B

INTERFACE

TEST PATTERN

(REG 0x573,

REG 0x551 TO

REG 0x558)

FRAME

CONSTRUCTION

JESD204B DATA

LINK LAYER TEST

PATTERNS

REG 0x574[2:0]

SCRAMBLER

1+ x14 +x15

(OPTIONAL)

A13

A12

A11

A10

MSB

LSB

MSB

LSB

a b c d e f g h i j

a b

i j a b

i j

JESD204B

LONG TRANSPORT

TEST PATTERN

REG 0x571[5]

Figure 98. ADC Output Data Path Showing Data Framing

TRANSPORT

LAYER

PHYSICAL

LAYER

DATA LINK

LAYER

OUTPUT

SAMPLE

CONSTRUCTION

FRAME

CONSTRUCTION

SCRAMBLER

ALIGNMENT

CHARACTER

GENERATION

8-BIT/10-BIT

ENCODER

CROSSBAR

MUX

SERIALIZER

PROCESSED

SAMPLES

FROM ADC

SYSREF±

SYNCINB±

Figure 99. Data Flow

FUNCTIONAL OVERVIEW

The block diagram in Figure 99 shows the flow of data through

the JESD204B hardware from the sample input to the physical

output. The processing can be divided into layers that are

derived from the open source initiative (OSI) model widely

used to describe the abstraction layers of communications

systems. These layers are the transport layer, data link layer,

and physical layer (serializer and output driver).

Transport Layer

The transport layer handles packing the data (consisting of

samples and optional control bits) into JESD204B frames that

are mapped to 8-bit octets. These octets are sent to the data link

layer. The transport layer mapping is controlled by rules derived

from the link parameters. Tail bits are added to fill gaps where

required. The following equation can be used to determine the

number of tail bits within a sample (JESD204B word):

T = N΄ – N – CS

Data Link Layer

The data link layer is responsible for the low level functions

of passing data across the link. These include optionally

scrambling the data, inserting control characters for multichip

synchronization/lane alignment/monitoring, and encoding

8-bit octets into 10-bit symbols. The data link layer is also

responsible for sending the initial lane alignment sequence

(ILAS), which contains the link configuration data used by the

receiver to verify the settings in the transport layer.

Physical Layer

The physical layer consists of the high speed circuitry clocked at

the serial clock rate. In this layer, parallel data is converted into

one, two, or four lanes of high speed differential serial data.

JESD204B LINK ESTABLISHMENT

The AD9690 JESD204B transmitter (Tx) interface operates in

Subclass 1 as defined in the JEDEC Standard 204B (July 2011

specification). The link establishment process is divided into the

following steps: code group synchronization and SYNCINB±,

initial lane alignment sequence, and user data and error correction.

Code Group Synchronization (CGS) and SYNCINB±

The CGS is the process by which the JESD204B receiver finds

the boundaries between the 10-bit symbols in the stream of

data. During the CGS phase, the JESD204B transmit block

transmits /K28.5/ characters. The receiver must locate /K28.5/

characters in its input data stream using clock and data recovery

(CDR) techniques.

The receiver issues a synchronization request by asserting the

SYNCINB± pin of the AD9690 low. The JESD204B Tx then begins

sending /K/ characters. Once the receiver has synchronized, it waits

for the correct reception of at least four consecutive /K/ symbols. It

then deasserts SYNCINB±. The AD9690 then transmits an ILAS

on the following local multiframe clock (LMFC) boundary.

For more information on the code group synchronization

phase, refer to the JEDEC Standard JESD204B, July 2011,

Section 5.3.3.1.

The SYNCINB± pin operation can also be controlled by the

SPI. The SYNCINB± signal is a differential dc-coupled LVDS

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