AT45DB642 datasheet(6/37 Pages) ATMEL

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AT45DB642

1638F–DFLSH–09/02

STATUS REGISTER READ: The status register can be used to determine the device’s

ready/busy status, the result of a Main Memory Page to Buffer Compare operation, or the

device density. To read the status register, an opcode of 57H or D7H must be loaded into the

device. After the opcode is clocked in, the 1-byte status register will be clocked out on the out-

put pins (SO or I/O7 - I/O0), starting with the next clock cycle. When using the serial interface,

the data in the status register, starting with the MSB (bit 7), will be clocked out on the SO pin

during the next eight clock cycles.

The five most-significant bits of the status register will contain device information, while the

remaining three least-significant bits are reserved for future use and will have undefined val-

ues. After the one byte of the status register has been clocked out, the sequence will repeat

itself (as long as CS remains low and SCK/CLK is being toggled). The data in the status regis-

ter is constantly updated, so each repeating sequence will output new data.

Ready/busy status is indicated using bit 7 of the status register. If bit 7 is a 1, then the device

is not busy and is ready to accept the next command. If bit 7 is a 0, then the device is in a busy

state. The user can continuously poll bit 7 of the status register by stopping SCK/CLK at a low

level once bit 7 has been output on the SO or I/O7 pin. The status of bit 7 will continue to be

output on the SO or I/O7 pin, and once the device is no longer busy, the state of the SO or

I/O7 pin will change from 0 to 1. There are eight operations that can cause the device to be in

a busy state: Main Memory Page to Buffer Transfer, Main Memory Page to Buffer Compare,

Buffer to Main Memory Page Program with Built-in Erase, Buffer to Main Memory Page Pro-

gram without Built-in Erase, Page Erase, Block Erase, Main Memory Page Program, and Auto

Page Rewrite.

The result of the most recent Main Memory Page to Buffer Compare operation is indicated

using bit 6 of the status register. If bit 6 is a 0, then the data in the main memory page matches

the data in the buffer. If bit 6 is a 1, then at least one bit of the data in the main memory page

does not match the data in the buffer.

The device density is indicated using bits 5, 4, 3 and 2 of the status register. For the

AT45DB642, the four bits are logical “1”s. The decimal value of these four binary bits does not

equate to the device density; the four bits represent a combinational code relating to differing

densities of DataFlash devices, allowing a total of sixteen different density configurations.

Program and

Erase Commands

BUFFER WRITE: Data can be clocked in from the input pins (SI or I/O7 - I/O0) into either

buffer 1 or buffer 2. To load data into either buffer, a 1-byte opcode, 84H for buffer 1 or 87H for

buffer 2, must be clocked into the device, followed by three address bytes comprised of 13

don’t care bits and 11 buffer address bits (BFA10 - BFA0). The 11 buffer address bits specify

the first byte in the buffer to be written. After the last address byte has been clocked into the

device, data can then be clocked in on subsequent clock cycles. If the end of the data buffer is

reached, the device will wrap around back to the beginning of the buffer. Data will continue to

be loaded into the buffer until a low-to-high transition is detected on the CS pin.

Status Register Format

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RDY/BUSY

COMP

111

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