COP840C datasheet(24/35 Pages) NSC

24 / 35 page

Memory Map

All RAM, ports and registers (except A and PC) are mapped

into data memory address space.

Address

Contents

00 to 2F

(820CJ)

On-chip RAM bytes (48 bytes)

00 to 6F

(840CJ)

On-chip RAM bytes (112 bytes)

30 to 7F

(820CJ)

Unused RAM Address Space (Reads as All

Ones)

70 to 7F

(840CJ)

Unused RAM Address Space (Reads as All

Ones)

80 to BF

Expansion Space for On-Chip EERAM

(Reads Undefined Data)

C0 to C7

Reserved

MIWU Edge Select Register (Reg:WKEDG)

MIWU Enable Register (Reg:WKEN)

MIWU Pending Register (Reg:WKPND)

Reserved

Control2 Register (CNTRL2)

WATCHDOG Register (WDREG)

WATCHDOG Counter (WDCNT)

Modulator Reload (MODRL)

Port L Data Register

Port L Configuration Register

Port L Input Pins (Read Only)

Reserved for Port L

Port G Data Register

Port G Configuration Register

Port G Input Pins (Read Only)

Port I Input Pins (Read Only)

D8 to DB

Reserved for Port C

Port D Data Register

DD to DF

Reserved for Port D

E0 to EF

On-Chip Functions and Registers

E0 to E7

Reserved for Future Parts

Reserved

MICROWIRE Shift Register

Timer Lower Byte

Timer Upper Byte

Timer1 Autoreload Register Lower Byte

Timer1 Autoreload Register Upper Byte

CNTRL1 Control Register

PSW Register

F0 to FF

On-Chip RAM Mapped as Registers

X Register

SP Register

B Register

Reading other unused memory locations will return unde-

fined data.

Addressing Modes

There are ten addressing modes, six for operand addressing

and four for transfer of control.

OPERAND ADDRESSING MODES

This is the “normal” addressing mode for the chip. The oper-

and is the data memory addressed by the B or X pointer.

OR DECREMENT

This addressing mode is used with the LD and X instruc-

tions. The operand is the data memory addressed by the B

or X pointer. This is a register indirect mode that automati-

cally post increments or post decrements the B or X pointer

after executing the instruction.

DIRECT

The instruction contains an 8-bit address field that directly

points to the data memory for the operand.

IMMEDIATE

The instruction contains an 8-bit immediate field as the oper-

and.

SHORT IMMEDIATE

This addressing mode issued with the LD B,# instruction,

where the immediate # is less than 16. The instruction con-

tains a 4-bit immediate field as the operand.

INDIRECT

This addressing mode is used with the LAID instruction. The

contents of the accumulator are used as a partial address

(lower 8 bits of PC) for accessing a data operand from the

program memory.

TRANSFER OF CONTROL ADDRESSING MODES

RELATIVE

This mode is used for the JP instruction with the instruction

field being added to the program counter to produce the next

instruction address. JP has a range from −31 to +32 to allow

a one byte relative jump (JP + 1 is implemented by a NOP in-

struction). There are no “blocks” or “pages” when using JP

since all 15 bits of the PC are used.

ABSOLUTE

This mode is used with the JMP and JSR instructions with

the instruction field of 12 bits replacing the lower 12 bits of

the program counter (PC). This allows jumping to any loca-

tion in the current 4k program memory segment.

ABSOLUTE LONG

This mode is used with the JMPL and JSRL instructions with

the instruction field of 15 bits replacing the entire 15 bits of

the program counter (PC). This allows jumping to any loca-

tion in the entire 32k program memory space.

INDIRECT

This mode is used with the JID instruction. The contents of

the accumulator are used as a partial address (lower 8 bits of

PC) for accessing a location in the program memory. The

contents of this program memory location serves as a partial

address (lower 8 bits of PC) for the jump to the next instruc-

tion.

COP840C Datasheet(PDF) 24 Page - National Semiconductor (TI)

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