COP840C datasheet(16/35 Pages) NSC

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Timer/Counter (Continued)

MODE 3. TIMER WITH CAPTURE REGISTER

Timer T1 can be used to precisely measure external fre-

quencies or events in this mode of operation. The timer T1

counts down at the instruction cycle rate. Upon the occur-

rence of a specified edge on the TIO pin the contents of the

timer T1 are copied into the register R1. Bits in the control

as a positive edge or as a negative edge. In this mode the

user can elect to be interrupted on the specified trigger edge

(

Figure 10).

TIMER PWM APPLICATION

Figure 11 shows how a minimal component D/A converter

can be built out of the Timer-Register pair in the Auto-Reload

mode. The timer is placed in the “Timer with auto reload”

mode and the TIO pin is selected as the timer output. At the

outset the TIO pin is set high, the timer T1 holds the on time

and the register R1 holds the signal off time. Setting TRUN

bit starts the timer which counts down at the instruction cycle

rate. The underflow toggles the TIO output and copies the off

time into the timer, which continues to run. By alternately

loading in the on time and the off time at each successive in-

terrupt a PWM frequency can be easily generated.

WATCHDOG

The device has an on-board 8-bit WATCHDOG timer. The

timer contains an 8-bit READ/WRITE down counter clocked

by an 8-bit prescaler. Under software control the timer can

be dedicated for the WATCHDOG or used as a general pur-

pose counter.

Figure 12 shows the WATCHDOG timer block

diagram.

MODE 1: WATCHDOG TIMER

The WATCHDOG is designed to detect user programs get-

ting stuck in infinite loops resulting in loss of program control

or “runaway” programs. The WATCHDOG can be enabled or

disabled (only once) after the device is reset as a result of

brown out reset or external reset. On power-up the WATCH-

DOG is disabled. The WATCHDOG is enabled by writing a

“1” to WDREN bit (resides in WDREG register). Once en-

abled, the user program should write periodically into the

8-bit counter before the counter underflows. The 8-bit

counter (WDCNT) is memory mapped at address 0CE Hex.

The counter is loaded with n-1 to get n counts. The counter

underflow resets the device, but does not disable the

WATCHDOG. Loading the 8-bit counter initializes the pres-

caler with FF Hex and starts the prescaler/counter. Prescaler

and counter are stopped upon counter underflow. Prescaler

and counter are each loaded with FF Hex when the device

goes into the HALT mode. The prescaler is used for crystal/

resonator start-up when the device exits the HALT mode

through Multi-Input Wakeup. In this case, the prescaler/

counter contents are changed.

DS011208-29

FIGURE 9. Timer in External Event Counter Mode

DS011208-25

FIGURE 10. Timer Capture Mode Block Diagram

DS011208-26

FIGURE 11. Timer Application

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