COP840C datasheet(17/35 Pages) NSC

17 / 35 page

WATCHDOG (Continued)

MODE 2: TIMER

In this mode, the prescaler/counter is used as a timer by

keeping the WDREN (WATCHDOG reset enable) bit at 0.

The counter underflow sets the WDUDF (underflow) bit and

the underflow does not reset the device. Loading the 8-bit

counter (load n-1 for n counts) sets the WDTEN bit (WATCH-

DOG Timer Enable) to “1”, loads the prescaler with FF, and

starts the timer. The counter underflow stops the timer. The

WDTEN bit serves as a start bit for the WATCHDOG timer.

This bit is set when the 8-bit counter is loaded by the user

program. The load could be as a result of WATCHDOG ser-

vice (WATCHDOG timer dedicated for WATCHDOG func-

tion) or write to the counter (WATCHDOG timer used as a

general purpose counter). The bit is cleared upon Brown Out

reset, WATCHDOG reset or external reset. The bit is not

memory mapped and is transparent to the user program.

TABLE 7. WATCHDOG Control/Status

HALT

EXT/BOR

Counter

Parameter

Mode

Reset

Load

(Note 10)

8-Bit Prescaler

8-Bit WD Counter

User Value

WDREN Bit

Unchanged

No Effect

WDUDF Bit

Unchanged

WDTEN Signal

Unchanged

Note 10: BOR is Brown Out Reset.

CONTROL/STATUS BITS

WDUDF: WATCHDOG Timer Underflow Bit

This bit resides in the CNTRL2 Register. The bit is set when

the WATCHDOG timer underflows. The underflow resets the

device if the WATCHDOG reset enable bit is set (WDREN =

1). Otherwise, WDUDF can be used as the timer underflow

flag. The bit is cleared upon Brown-Out reset, external reset,

load to the 8-bit counter, or going into the HALT mode. It is a

read only bit.

WDREN: WD Reset Enable

WDREN bit resides in a separate register (bit 0 of WDREG).

This bit enables the WATCHDOG timer to generate a reset.

The bit is cleared upon Brown Out reset, or external reset.

The bit under software control can be written to only once

(once written to, the hardware does not allow the bit to be

changed during program execution).

WDREN = 1 WATCHDOG reset is enabled.

WDREN = 0 WATCHDOG reset is disabled.

Table 7 shows the impact of Brown Out Reset, WATCHDOG

Reset, and External Reset on the Control/Status bits.

COP840C Datasheet(PDF) 17 Page - National Semiconductor (TI)

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