TUSB3410 datasheet(54/92 Pages) TI

54 / 92 page

7–8

BIT

FUNCTION

RESET

NAME

LCD

During loopback, this bit reflects the status of MCR[3] (see Figure 7–1).

LCD = 0

CD input is high

CD input is low

7.1.9

DLL: Divisor Register Low Byte (Addr:FFA7)

This register contains the low byte of the baud-rate divisor.

765

R/W

BIT

NAME

RESET

FUNCTION

7–0

D[7:0]

08h

Low-byte value of the 16-bit divisor for generation of the baud clock in the baud-rate generator.

7.1.10 DLH: Divisor Register High Byte (Addr:FFA8)

This register contains the high byte of the baud-rate divisor.

765

D15

D14

D13

D12

D11

D10

R/W

BIT

NAME

RESET

FUNCTION

7–0

D[15:8]

00h

High-byte value of the 16-bit divisor for generation of the baud clock in the baud-rate generator.

7.1.11 Baud-rate Calculation

The following formulas are used to calculate the baud-rate clock and the divisors. The baud-rate clock is derived from

the 96-MHz master clock (dividing by 6.5). The table below presents the divisors used to achieve the desired baud

rates, together with the associate rounding errors.

Baud CLK

+ 96 MHz

6.5

+ 14.76923077 MHz

Divisor

+ 14.76923077

106

Baud Rate

TUSB3410 Datasheet(PDF) 54 Page - Texas Instruments

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