TUSB3410 datasheet(58/92 Pages) TI

58 / 92 page

7–12

7.2.5

Xon/Xoff Receiver Flow Control

To enable Xon/Xoff flow control, certain MCR bits must be set as follows: MCR[5] = 1 and MCR[7:6] = 0. In this mode,

the Xon/Xoff bytes are transmitted to an external sending device to control the device’s transmission. When the

high-level mark (of the FIFO) is reached, the Xoff byte is transmitted, signaling to an external sending device to halt

its transfer. Conversely, when the low-level mark is reached, the Xon byte is transmitted, signaling to an external

sending device to resume its transfer. The data transfer from the FIFO to X-/Y-buffer is performed by the DMA

controller.

7.2.6

Xon/Xoff Transmit Flow Control

To enable Xon/Xoff flow control, certain MCR bits must be set as follows: MCR[5] = 1 and MCR[7:6] = 0. In this mode,

the incoming data are compared to the XON and XOFF registers. If a match to XOFF is detected, the DMA is paused.

If a match to XON is detected, the DMA resumes. Meanwhile, the UBM is transferring data from the host to the

X-buffer. The MCU does not switch the buffers unless the Y-buffer is empty and the X-buffer is full. When Xon is

detected, the DMA resumes the transfer.

TUSB3410 Datasheet(PDF) 58 Page - Texas Instruments