TUSB3410 datasheet(66/92 Pages) TI

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10–2

10.1.2 I2CADR: I2C Address Register (Addr:FFF3)

This register holds the device address and the read/write command bit.

765

R/W

BIT

NAME

RESET

FUNCTION

R/W

Read/write command bit

R/W = 0

R/W = 1

Write operation

Read operation

7–1

A[6:0]

Seven address bits for device addressing

10.1.3 I2CDAI: I2C Data-Input Register (Addr:FFF2)

This register holds the received data from an external device.

765

R/O

BIT

NAME

RESET

FUNCTION

7–0

D[7:0]

8-bit input data from an I2C device

10.1.4 I2CDAO: I2C Data-Output Register (Addr:FFF1)

This register holds the data to be transmitted to an external device. Writing to this register starts the transfer on the

SDA line.

765

W/O

BIT

NAME

RESET

FUNCTION

7–0

D[7:0]

8-bit output data to an I2C device

10.2 Random-Read Operation

A random read requires a dummy byte-write sequence to load in the data word address. Once the device-address

word and the data-word address are clocked out and acknowledged by the device, the MCU starts a current-address

sequence. The following describes the sequence of events to accomplish this transaction.

Device Address + EPROM [High Byte]

•

The MCU sets I2CSTA[SRD] = 0. This forces the I2C controller not to generate a stop condition after the

contents of the I2CDAI register are received.

•

The MCU sets I2CSTA[SWR] = 0. This forces the I2C controller not to generate a stop condition after the

contents of the I2CDAO register are transmitted.

•

The MCU writes the device address (R/W bit = 0) to the I2CADR register (write operation)

•

The MCU writes the high byte of the E2PROM address into the I2CDAO register (this starts the transfer on

the SDA line).

•

The TXE bit in the I2CSTA register is cleared (indicates busy).

•

The content of the I2CADR register is transmitted to E2PROM (preceded by start condition on SDA).

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