TUSB3410 datasheet(61/92 Pages) TI

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9–1

9 Interrupts

9.1

8052 Interrupt and Status Registers

All 8052 standard, five interrupt sources are preserved. SIE is the standard interrupt-enable register that controls the

five interrupt sources. All the additional interrupt sources are ORed together to generate EX0. The XINTO signal is

provided to interrupt an external MCU (see Figure 9–1).

Table 9–1. 8052 Interrupt Location Map

INTERRUPT SOURCE

DESCRIPTION

START ADDRESS

COMMENTS

UART interrupt

0023H

ET1

Timer-1 interrupt

001BH

EX1

External interrupt-1

0013H

ET0

Timer-0 interrupt

000BH

EX0

External interrupt-0

0003H

Used for all internal peripherals

Reset

0000H

9.1.1

8052 Standard Interrupt Enable (SIE) Register

765

ET1

EX1

ET0

EX0

R/W

BIT

NAME

RESET

FUNCTION

EX0

Enable or disable external interrupt-0

EX0 = 1

External interrupt-0 is disabled

External interrupt-0 is enabled

ET0

Enable or disable timer-0 interrupt

ET0 = 0

ET0 = 1

Timer-0 interrupt is disabled

Timer-0 interrupt is enabled

EX1

Enable or disable external interrupt-1

EX1 = 0

EX1 = 1

External interrupt-1 is disabled

External interrupt-1 is enabled

ET1

Enable or disable timer-1 interrupt

ET1 = 0

EX1 = 1

Timer-1 interrupt is disabled

Timer-1 interrupt is enabled

Enable or disable serial port interrupts

ES = 0

ES = 1

Serial-port interrupt is disabled

Serial-port interrupt is enabled

5, 6

RSV

Reserved

Enable or disable all interrupts (global disable)

EA = 0

EA = 1

Disable all interrupts

Each interrupt source is individually controlled

9.1.2

Additional Interrupt Sources

All nonstandard 8052 interrupts (DMA, I2C, etc.) are ORed to generate an internal INT0. Note, the external INT0 is

not used. Furthermore, the INT0 must be programmed as an active low-level interrupt (not edge triggered). A vector

interrupt register is provided to identify all interrupt sources (see VECINT: vector-interrupt register). Up to 64 interrupt

vectors are provided. It is the responsibility of the MCU to read the vector and dispatch to the proper interrupt routine.

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