TSC2102 datasheet(23/54 Pages) TI

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TSC2102

SLAS379A− APRIL 2003 − REVISED JUNE 2004

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D LEFT-JUSTIFIED MODE

In left−justified mode, the MSB of the right channel is valid on the rising edge of the BCLK following the falling edge of

LRCK. Similarly the MSB of the left channel is valid on the rising edge of the BCLK following the rising edge of LRCK.

BCLK

LRCK

DIN

n−1

1/fs

LSB

MSB

Left Channel

Right Channel

n−1

n−2

Figure 19. Timing Diagram for Left-Justified Mode

D I2S MODE

In I2S mode, the MSB of the left channel is valid on the second rising edge of the BCLK after the falling edge of LRCK.

Similarly, the MSB of the right channel is valid on the second rising edge of the BCLK after the rising edge of LRCK.

BCLK

LRCK

DIN

n−1

1/fs

LSB

MSB

Left Channel

Right Channel

1 clock before MSB

n−2

Figure 20. Timing Diagram for I2S Mode

D DSP MODE

In DSP mode, the falling edge of LRCK starts the data transfer with the left channel data first and immediately followed

by the right channel data. Each data bit is valid on the falling edge of BCLK.

BCLK

LRCK

DIN

n−1

1/fs

LSB

MSB

Left Channel

Right Channel

n−1

MSB

LSB

n−2

MSB

LSB

Figure 21. Timing Diagram for DSP Mode

TSC2102 Datasheet(PDF) 23 Page - Texas Instruments

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