TSC2102 datasheet(27/54 Pages) TI

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TSC2102

SLAS379A− APRIL 2003 − REVISED JUNE 2004

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KEYCLICK

A special circuit has also been included for inserting a square-wave signal into the analog output signal path based on

contains bits that control the amplitude, frequency, and duration of the square−wave signal. The frequency of the signal

can be varied from 62.5 Hz to 8 kHz and its duration can be programmed from 2 periods to 32 periods. Whenever this

register is written, the square wave is generated and coupled into the audio output, going to both the outputs. The keyclick

enable bit D15 of control register 04H/Page2 is reset after the duration of keyclick is played out. This capability is available

even when the DAC is powered down.

SPI DIGITAL INTERFACE

All TSC2102 control registers are programmed through a standard SPI bus. The SPI allows full-duplex, synchronous, serial

communication between a host processor (the master) and peripheral devices (slaves). The SPI master generates the

synchronizing clock and initiates transmissions. The SPI slave devices depend on a master to start and synchronize

transmissions.

A transmission begins when initiated by a master SPI. The byte from the master SPI begins shifting in on the slave SPIDIN

(MOSI) pin under the control of the master serial clock. As the byte shifts in on the SPIDIN pin, a byte shifts out on the

SPIDOUT (MISO) pin to the master shift register.

The idle state of the serial clock for the TSC2102 is low, which corresponds to a clock polarity setting of 0 (typical

microprocessor SPI control bit CPOL = 0). The TSC2102 interface is designed so that with a clock phase bit setting of 1

(typical microprocessor SPI control bit CPHA = 1), the master begins driving its MOSI pin and the slave begins driving its

SPIDOUT pin on the first serial clock edge. The SS pin can remain low between transmissions; however, the TSC2102

only interprets command words which are transmitted after the falling edge of SS.

TSC2102 COMMUNICATION PROTOCOL

The TSC2102 is entirely controlled by registers. Reading and writing these registers is controlled by an SPI master and

accomplished by the use of a 16-bit command, which is sent prior to the data for that register. The command is constructed

as shown in Figure 23.

The command word begins with a R/W bit, which specifies the direction of data flow on the SPI serial bus. The following

4 bits specify the page of memory this command is directed to, as shown in Table 2. The next six bits specify the register

address on that page of memory to which the data is directed. The last five bits are reserved for future use and should be

written only with zeros.

TSC2102 Datasheet(PDF) 27 Page - Texas Instruments