AM1705DPTP3 datasheet(53/165 Pages) TI1

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AM1705

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SPRS657E – FEBRUARY 2010 – REVISED JUNE 2014

6.8

General-Purpose Input/Output (GPIO)

The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.

When configured as an output, a write to an internal register can control the state driven on the output pin.

When configured as an input, the state of the input is detectable by reading the state of an internal

interrupt/event generation modes. The GPIO peripheral provides generic connections to external devices.

The GPIO pins are grouped into banks of 16 pins per bank (i.e., bank 0 consists of GPIO [0:15]).

The device GPIO peripheral supports the following:

•

External Interrupt and DMA request Capability

–

Every GPIO pin may be configured to generate an interrupt request on detection of rising and/or

falling edges on the pin.

–

The interrupt requests within each bank are combined (logical or) to create eight unique bank level

interrupt requests.

–

The bank level interrupt service routine may poll the INTSTATx register for its bank to determine

which pin(s) have triggered the interrupt.

–

GPIO Banks 0, 1, 2, 3, 4, 5, 6, and 7 Interrupts assigned to ARM INTC Interrupt Requests 42, 43,

44, 45, 46, 47, 48, and 49 respectively

–

Additionally, GPIO Banks 0, 1, 2, 3, 4, and 5 Interrupts assigned to EDMA events 6, 7, 22, 23, 28,

and 29 respectively.

•

Set/clear functionality: Firmware writes 1 to corresponding bit position(s) to set or to clear GPIO

signal(s). This allows multiple firmware processes to toggle GPIO output signals without critical section

protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to

anther process during GPIO programming).

•

Separate Input/Output registers

•

Output register in addition to set/clear so that, if preferred by firmware, some GPIO output signals can

be toggled by direct write to the output register(s).

•

Output register, when read, reflects output drive status. This, in addition to the input register reflecting

pin status and open-drain I/O cell, allows wired logic be implemented.

The memory map for the GPIO registers is shown in Table 6-8.

Peripheral Information and Electrical Specifications

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