AM1705DPTP3 datasheet(71/165 Pages) TI1

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AM1705

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SPRS657E – FEBRUARY 2010 – REVISED JUNE 2014

6.11.4 EMIFB Electrical Data/Timing

Table 6-23. EMIFB SDRAM Interface Timing Requirements

CVDD = 1.3 V(1)

CVDD = 1.2V(2)

UNI

NO.

MIN

MAX

MIN

MAX

Input setup time, read data valid on EMB_D[31:0] before

t(DV-CLKH)

0.59

0.8

EMB_CLK rising

Input hold time, read data valid on EMB_D[31:0] after

th(CLKH-DIV)

1.25

1.5

EMB_CLK rising

(1)

Commercial (default), Industrial and Extended temperature range rated devices for 456 MHz max CPU operating frequency as

applicable to the device

(2)

Commercial (default), Industrial, Extended and Automotive temperature range rated devices for 400/375/300/266/200 MHz max CPU

operating frequencies as applicable to the device

Table 6-24. EMIFB SDRAM Interface Switching Characteristics for Commercial (Default) Temperature

Range

CVDD = 1.3 V(1)

CVDD = 1.2V(2)

UNI

NO.

PARAMETER

MIN

MAX

MIN

MAX

tc(CLK)

Cycle time, EMIF clock EMB_CLK

6.579

7.5

tw(CLK)

Pulse width, EMIF clock EMB_CLK high or low

2.63

td(CLKH-CSV)

Delay time, EMB_CLK rising to EMB_CS[0] valid

4.25

5.1

toh(CLKH-CSIV)

Output hold time, EMB_CLK rising to EMB_CS[0] invalid

1.1

td(CLKH-DQMV)

Delay time, EMB_CLK rising to EMB_WE_DQM[3:0] valid

4.25

5.1

Output hold time, EMB_CLK rising to EMB_WE_DQM[3:0]

toh(CLKH-DQMIV)

1.1

invalid

Delay time, EMB_CLK rising to EMB_A[12:0] and

td(CLKH-AV)

4.25

5.1

EMB_BA[1:0] valid

Output hold time, EMB_CLK rising to EMB_A[12:0] and

toh(CLKH-AIV)

1.1

EMB_BA[1:0] invalid

td(CLKH-DV)

Delay time, EMB_CLK rising to EMB_D[31:0] valid

4.25

5.1

toh(CLKH-DIV)

Output hold time, EMB_CLK rising to EMB_D[31:0] invalid

1.1

td(CLKH-RASV)

Delay time, EMB_CLK rising to EMB_RAS valid

4.25

5.1

toh(CLKH-RASIV)

Output hold time, EMB_CLK rising to EMB_RAS invalid

1.1

td(CLKH-CASV)

Delay time, EMB_CLK rising to EMB_CAS valid

4.25

5.1

toh(CLKH-CASIV)

Output hold time, EMB_CLK rising to EMB_CAS invalid

1.1

td(CLKH-WEV)

Delay time, EMB_CLK rising to EMB_WE valid

4.25

5.1

toh(CLKH-WEIV)

Output hold time, EMB_CLK rising to EMB_WE invalid

1.1

tdis(CLKH-DHZ)

Delay time, EMB_CLK rising to EMB_D[31:0] tri-stated

4.25

5.1

t(CLKH-DLZ)

Output hold time, EMB_CLK rising to EMB_D[31:0] driving

1.1

(1)

Commercial (default) temperature range rated devices for 456 MHz max CPU operating frequency as applicable to the device

(2)

Commercial (default) temperature range rated devices for 400/375/300/266/200 MHz max CPU operating frequencies as applicable to

the device

Table 6-25. EMIFB SDRAM Interface Switching Characteristics for Industrial, Extended, and Automotive

Temperature Ranges

CVDD = 1.3 V(1)

CVDD = 1.2V(2)

UNI

NO.

PARAMETER

MIN

MAX

MIN

MAX

tc(CLK)

Cycle time, EMIF clock EMB_CLK

6.579

7.5

tw(CLK)

Pulse width, EMIF clock EMB_CLK high or low

2.63

td(CLKH-CSV)

Delay time, EMB_CLK rising to EMB_CS[0] valid

4.25

5.1

toh(CLKH-CSIV)

Output hold time, EMB_CLK rising to EMB_CS[0] invalid

1.1

0.9

(1)

Industrial temperature range rated devices for 456 MHz max CPU operating frequency as applicable to the device

(2)

Industrial, Extended and Automotive temperature range rated devices for 400/375/300/266/200 MHz max CPU operating frequencies as

applicable to the device

Peripheral Information and Electrical Specifications

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