AM4372 datasheet(3/266 Pages) TI1

3 / 266 page

AM4376, AM4377, AM4378, AM4379

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SPRS851C – JUNE 2014 – REVISED APRIL 2016

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Product Folder Links: AM4376 AM4377 AM4378 AM4379

Device Overview

•

McSPI3 and McSPI4 Support up to Two

Chip Selects

•

Up to 48 MHz

– One Quad-SPI

•

Supports eXecute In Place (XIP) from Serial

NOR FLASH

– One Dallas 1-Wire® and HDQ Serial Interface

– Up to Three MMC, SD, and SDIO Ports

•

1-, 4-, and 8-Bit MMC, SD, and SDIO Modes

•

1.8- or 3.3-V Operation on All Ports

•

Up to 48-MHz Clock

•

Supports Card Detect and Write Protect

•

Complies With MMC4.3 and SD and SDIO

2.0 Specifications

– Up to Three I2C Master and Slave Interfaces

•

Standard Mode (up to 100 kHz)

•

Fast Mode (up to 400 kHz)

– Up to Six Banks of General-Purpose I/O (GPIO)

•

32 GPIOs per Bank (Multiplexed With Other

Functional Pins)

•

GPIOs Can be Used as Interrupt Inputs (up

to Two Interrupt Inputs per Bank)

– Up to Three External DMA Event Inputs That

Can Also be Used as Interrupt Inputs

– Twelve 32-Bit General-Purpose Timers

•

DMTIMER1 is a 1-ms Timer Used for

Operating System (OS) Ticks

•

DMTIMER4–DMTIMER7 are Pinned Out

– One Public Watchdog Timer

– One Free-Running, High-Resolution 32-kHz

Counter (synctimer32K)

– One Secure Watchdog Timer (Avaliable Only on

AM437xHS Devices)

– SGX530 3D Graphics Engine

•

Tile-Based Architecture Delivering up to 20M

Poly/sec

•

Universal Scalable Shader Engine is a

Multithreaded Engine Incorporating Pixel and

Vertex Shader Functionality

•

Advanced Shader Feature Set in Excess of

Microsoft VS3.0, PS3.0, and OGL2.0

•

Industry Standard API Support of Direct3D

Mobile, OGL-ES 1.1 and 2.0, and OpenVG

1.0

•

Fine-Grained Task Switching, Load

Balancing, and Power Management

•

Advanced Geometry DMA-Driven Operation

for Minimum CPU Interaction

•

Programmable High-Quality Image Anti-

Aliasing

•

Fully Virtualized Memory Addressing for OS

Operation in a Unified Memory Architecture

– Display Subsystem

•

Display Modes

–

Programmable Pixel Memory Formats

(Palletized: 1-, 2-, 4-, and 8-Bits Per

Pixel; RGB 16- and 24-Bits Per Pixel; and

YUV 4:2:2)

–

256- × 24-Bit Entries Palette in RGB

–

Up to 2048 × 2048 Resolution

•

Display Support

–

Four Types of Displays Are Supported:

Passive and Active Colors; Passive and

Active Monochromes

–

4- and 8-Bit Monochrome Passive Panel

Interface Support (15 Grayscale Levels

Supported Using Dithering Block)

–

RGB 8-Bit Color Passive Panel Interface

Support (3,375 Colors Supported for

Color Panel Using Dithering Block)

–

RGB 12-, 16-, 18-, and 24-Bit Active

Panel Interface Support (Replicated or

Dithered Encoded Pixel Values)

–

Remote Frame Buffer (Embedded in the

LCD Panel) Support Through the RFBI

Module

–

Partial Refresh of the Remote Frame

Buffer Through the RFBI Module

–

Partial Display

–

Multiple Cycles Output Format on 8-, 9-,

12-, and 16-Bit Interface (TDM)

•

Signal Processing

–

Overlay and Windowing Support for One

Graphics Layer (RGB or CLUT) and Two

Video Layers (YUV 4:2:2, RGB16, and

RGB24)

–

RGB 24-Bit Support on the Display

Interface, Optionally Dithered to RGB

‑Bit Pixel Output Plus 6-Bit Frame Rate

Control (Spatial and Temporal)

–

Transparency Color Key (Source and

Destination)

–

Synchronized Buffer Update

–

Gamma Curve Support

–

Multiple-Buffer Support

–

Cropping Support

–

Color Phase Rotation

– Two 12-Bit SAR ADCs (ADC0, ADC1)

•

867K Samples Per Second

•

Input Can Be Selected from Any of the Eight

Analog Inputs Multiplexed Through an 8:1

Analog Switch

•

ADC0 Can Be Configured to Operate as a

‑, 5-, or 8-Wire Resistive Touch Screen

Controller (TSC)

– Up to Three 32-Bit eCAP Modules

•

Configurable as Three Capture Inputs or

Three Auxiliary PWM Outputs

– Up to Six Enhanced eHRPWM Modules

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