| Electronic Components Datasheet Search |
|
AM4372 Datasheet(PDF) 73 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
AM4372 Datasheet(HTML) 73 Page - Texas Instruments |
|
73 / 266 page ![]() 73 AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851C – JUNE 2014 – REVISED APRIL 2016 Submit Documentation Feedback Product Folder Links: AM4376 AM4377 AM4378 AM4379 Terminal Configuration and Functions Copyright © 2014–2016, Texas Instruments Incorporated Table 4-27. DDR Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4] ddr_d20 DDR SDRAM DATA IO V1 ddr_d21 DDR SDRAM DATA IO W4 ddr_d22 DDR SDRAM DATA IO W5 ddr_d23 DDR SDRAM DATA IO W6 ddr_d24 DDR SDRAM DATA IO Y2 ddr_d25 DDR SDRAM DATA IO Y3 ddr_d26 DDR SDRAM DATA IO Y4 ddr_d27 DDR SDRAM DATA IO AA3 ddr_d28 DDR SDRAM DATA IO AB2 ddr_d29 DDR SDRAM DATA IO AB1 ddr_d30 DDR SDRAM DATA IO AC1 ddr_d31 DDR SDRAM DATA IO AC2 ddr_dqm0 DDR WRITE ENABLE / DATA MASK FOR DATA[7:0] O F4 ddr_dqm1 DDR WRITE ENABLE / DATA MASK FOR DATA[15:8] O H2 ddr_dqm2 DDR WRITE ENABLE / DATA MASK FOR DATA[23:16] O V6 ddr_dqm3 DDR WRITE ENABLE / DATA MASK FOR DATA[31:24] O Y1 ddr_dqs0 DDR DATA STROBE FOR DATA[7:0] (Differential+) IO F2 ddr_dqs1 DDR DATA STROBE FOR DATA[15:8] (Differential+) IO J2 ddr_dqs2 DDR DATA STROBE FOR DATA[23:16] (Differential+) IO W1 ddr_dqs3 DDR DATA STROBE FOR DATA[31:24] (Differential+) IO AA1 ddr_dqsn0 DDR DATA STROBE FOR DATA[7:0] (Differential-) IO F1 ddr_dqsn1 DDR DATA STROBE FOR DATA[15:8] (Differential-) IO J1 ddr_dqsn2 DDR DATA STROBE FOR DATA[23:16] (Differential-) IO W2 ddr_dqsn3 DDR DATA STROBE FOR DATA[31:24] (Differential-) IO AA2 ddr_nck DDR SDRAM CLOCK (Differential-) O M1 ddr_odt0 DDR SDRAM ODT0 O U1 ddr_odt1 DDR SDRAM ODT1 O U2 ddr_rasn DDR SDRAM ROW ADDRESS STROBE (ACTIVE LOW) O N2 ddr_resetn DDR SDRAM RESET (only for DDR3) O T1 ddr_vref Voltage Reference AP (1) T6 ddr_vtp External Resistor for Impedance Training I (2) AC3 ddr_wen DDR SDRAM WRITE ENABLE (ACTIVE LOW) O N4 (1) This terminal is an analog input used to set the switching threshold of the DDR input buffers to (VDDS_DDR / 2). (2) This terminal is an analog passive signal that connects to an external 49.9 Ω 1%, 20mW reference resistor which is used to calibrate the DDR input/output buffers. Table 4-28. General Purpose Memory Controller (GPMC) Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4] gpmc_a0 GPMC Address O B22, C3 gpmc_a1 GPMC Address O A21, B23, C5 gpmc_a2 GPMC Address O A23, B21, C6 gpmc_a3 GPMC Address O A22, A4, C21 gpmc_a4 GPMC Address O A20, A24, D7 gpmc_a5 GPMC Address O B20, C10, E7 gpmc_a6 GPMC Address O C20, E8 gpmc_a7 GPMC Address O E19, F6 gpmc_a8 GPMC Address O B23, F7 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |