AD1985

Rev. A | Page 28 of 48

Extended Audio Status and Control Register (Index 0x2A)

Reg

Num

Name

D15

D14 D13 D12 D11 D10 D9 D8

D7

D6

D5

D4

D3 D2

D1

D0

Default

0x2A Extended

Audio

Stat/Ctrl

VFORCE X

PRK PRJ PRI SPCV X

ASCLDAC ASCSDAC ASCCDAC SPSA1 SPSA0 X

ASCSPDF ASCDRA ASCVRA 0xXXXX

The extended audio status and control register is a read/write register that provides status and control of the extended audio features.

ASCVRA

Variable Rate Audio (Read/Write).

ASCVRA = 0 sets fixed sample rate audio at 48 kHz (reset default).

ASCVRA = 1 enables variable rate audio mode (enables sample rate registers and AC ’97 SLOTREQ signaling).

ASCDRA

Double Rate Audio.

ASCDRA = 1 enables double-rate audio mode in which data from PCM L and PCM R in output Slots 3 and 4 is used in

conjunction with PCM L (n + 1) and PCM R (n + 1) data to provide DAC streams at twice the sample rate designated by the PCM

Front Sample Rate Control Register.

When using the double rate audio only the front DACs are supported, and all other DACs (surround, center and LFE) are

automatically powered down.

Note that ASCDRA can be used without ASCVRA; in that case, the converter rates are forced to 96 kHz if ASCDRA = 1.

ASCSPDF

SPDIF Transmitter Subsystem Enable/Disable Bit (Read/Write).

ASCSPDF = 1 enables the SPDIF transmitter.

ASCSPDF = 0 disables the SPDIF transmitter (default).

This bit is also used to validate that the SPDIF transmitter output is actually enabled.

The ASCSPDF bit is only allowed to be set high if the Pin 48 (SPDIF) is pulled down at power-up, enabling the codec transmitter

logic. If the SPDIF pin is floating or pulled high at power-up, the transmitter logic is disabled, and therefore, the ASCSPDF bit

returns a low, indicating that the SPDIF transmitter is not available. This bit must always be read back to verify that the SPDIF

transmitter is actually enabled.

SPSA[1,0]

SPDIF Slot Assignment Bits (Read/Write).

These bits control the SPDIF slot assignment and respective defaults, depending on the codec ID configuration (see the the AC

‘97 2.3 AMAP Compliant Default SPDIF Slot Assignments table for more information.)

ASCCDAC

Center DAC Status (Read-Only).

ASCCDAC = 1 indicates the PCM center DAC is ready.

ASCSDAC

Surround DAC Status. (Read-only.)

ASCSDAC = 1 Indicates the PCM surround DACs are ready.

ASCLDAC

LFE DAC Status (Read-Only).

ASCLDAC = 1 indicates the PCM LFE DAC is ready.

SPCV

SPDIF Configuration Valid (Read-Only). Indicates the status of the SPDIF transmitter subsystem, enabling the driver to

determine if the currently programmed SPDIF configuration is supported. SPCV is always valid, independent of the SPDIF

enable bit status.

SPCV = 0 indicates current SPDIF configuraton (SPSA, SPSR, DAC slot rate, DRS) is not valid (not supported).

SPCV = 1 indicates current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is valid (is supported).

PRI

Center DAC Power-Down (Read/Write).

PRI = 1 mutes the PCM center DAC. Essentially, PRI + PRK = powered off center/LFE DACs.

PRJ

Surround DACs Power-Down (Read/Write).

PRJ = 1 turns off the PCM surround DACs.

PRK

LFE DAC Power-Down (Read/Write).

PRK = 1 mutes the PCM LFE DAC. Essentially, PRI + PRK = powered off center/LFE DACs.

VFORCE

Validity Force Bit. (Reset Default = 0).

When asserted, this bit forces the SPDIF stream Validity flag (Bit <28> within each SPDIF L/R subframe) to be controlled by the

V bit (D15) in Register 0x3A (SPDIF control register).

VFORCE = 0 and V = 0: The Validity bit is managed by the codec error detection logic.

VFORCE = 0 and V = 1: The Validity bit is forced high, indicating subframe data is invalid.

VFORCE = 1 and V = 0: The Validity bit is forced low, indicating subframe data is valid.

VFORCE = 1 and V = 1: The Validity bit is forced high, indicating subframe data is invalid.