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Rev. A | Page 29 of 48

AC ‘97 2.3 AMAP Compliant Default SPDIF Slot Assignments

Codec ID

Function

SPSA = 00

SPSA = 01

SPSA = 10

SPSA = 11

00

2-ch Primary with SPDIF

3 and 4

7 and 8 [default]

6 and 9

10 and 11

00

4-ch Primary with SPDIF

3 and 4

7 and 8

6 and 9 (default)

10 and 11

00

6-ch Primary with SPDIF

3 and 4

7 and 8

6 and 9

10 and 11 (default)

01

+2-ch Secondary with SPDIF

3 and 4

7 and 8

6 and 9 (default)

01

+4-ch Secondary with SPDIF

3 and 4

7 and 8

6 and 9

10 and 11 (default)

10

+2-ch Secondary with SPDIF

3 and 4

7 and 8

6 and 9 (default)

10

+4-ch Secondary with SPDIF

3 and 4

7 and 8

6 and 9

10 and 11 (default)

11

+2-ch Secondary with SPDIF

3 and 4

7 and 8

6 and 9

10 and 11 (default)

PCM Front DAC Rate Register (Index 0x2C)

Reg Num Name

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x2C

PCM Front DAC Rate

SRF15 SRF14 SRF13 SRF12 SRF11 SRF10 SRF9 SRF8 SRF7 SRF6 SRF5 SRF4 SRF3 SRF2 SRF1 SRF0 0xBB80

This read/write sample rate control register contains 16-bit unsigned values, representing the rate of operation in Hz.

SR[15:0]

Sample Rate. The sampling frequency range is from 7 kHz (0x1B58) to 48 kHz (0xBB80) in 1 Hz increments. The codec may

not function correctly if frequencies are written outside this range. If 0 is written to ASCVRA (Reg 0x2A), then the sample

rate is reset to 48 kHz.

PCM Surround DAC Rate Register (Index 0x2E)

Reg Num

Name

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x2E

PCM Surr DAC Rate

SRS15 SRS14 SRS13 SRS12 SRS11 SRS10 SRS9 SRS8 SRS7 SRS6 SRS5 SRS4 SRS3 SRS2 SRS1 SRS0 0xBB80

This read/write sample rate control register contains 16-bit unsigned values, representing the rate of operation in Hz.

This register sets the sample rate for the Surround DAC. This register’s reset default is to be locked to the PCM front DAC sample rate

register (0x2C). To unlock this register, Bit SSRU in Register 0x76 must be asserted.

SRS[15:0]

Sample Rate. The sampling frequency range is from 7 kHz (0x1B58) to 48 kHz (0xBB80) in 1 Hz increments. The codec

may not function correctly if frequencies are written outside this range. If 0 is written to ASCVRA (Reg 0x2A), then the

sample rate is reset to 48 kHz.

PCM LFE/Center DAC Rate Register (Index 0x30)

Reg Num NAME

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x30

PCM LFE/C DAC

Rate

SRCL15 SRCL14 SRCL13 SRCL12 SRCL11 SRCL10 SRCL9 SRCL8 SRCL7 SRCL6 SRCL5 SRCL4 SRCL3 SRCL2 SRCL1 SRCL0 0xBB80

This read/write sample rate control register contains 16-bit unsigned values, representing the rate of operation in Hz.

This register sets the sample rate for the LFE DAC and center DAC. This register’s reset default is to be locked to the PCM front DAC

sample rate register (0x2C). To unlock this register, Bit SSRU in Register 0x76 must be asserted.

SRCL[15:0]

Sample Rate. The sampling frequency range is from 7 kHz (0x1B58) to 48 kHz (0xBB80) in 1 Hz increments. The codec

may not function correctly if frequencies are written outside this range. If 0 is written to ASCVRA (Register 0x2A), then

the sample rate is reset to 48 kHz.