AD1985

Rev. A | Page 38 of 48

Serial Configuration (Index 0x74)

Reg

Num

Name

D15

D14

D13

D12

D11

D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x74

Serial

Config.

SLOT16 REGM2 REGM1 REGM0 REGM3 DRF OMS CHEN SPOVR LBKS1 LBKS0 INTS CSWP SPAL SPDZ SPLNK 0x1001

Note: This register will only reset bits CSWP (D3), LBKS[1:0] (D[6:5]), and OMS (D9) when Register 0x00 is written to (soft reset). All bits are reset on a hard or hardware

reset.

SPLNK

SPDIF Link. This bit enables the SPDIF to link with the front DACs for data requesting.

0: SPDIF and front DACs are not linked.

1: SPDIF and front DACs are linked and receive same data requests. (Reset default.)

SPDZ

SPDIF DACZ.

0: Repeat last sample out the SPDIF stream if FIFO underruns. (Reset default.)

1: Forces midscale sample out the SPDIF stream if FIFO underruns.

SPAL

SPDIF ADC Loop-Around.

0: SPDIF transmitter is connected to the AC Link stream. (Reset default.)

1: SPDIF transmitter is connected to the digital ADC stream, not the AC Link.

CSWP

Swap the Center/LFE Channels. Some systems have a swapped external connection for the center and LFE Channels.

Setting this bit will swap these channels internal to the codec. Setting this bit also swaps the definitions of the center/LFE

volume controls in Register 0x36.

INTS

Interrupt Mode Select. This bit selects the audio interrupt implementation path.

0: Slot 12, Bit 0 (modem interrupt) (reset default).

1: Slot 6, Valid Bit (MIC ADC interrupt).

Note: This bit does not generate an interrupt. Rather, it steers the path of the generated interrupt.

LBKS[1:0]

Loop-Back Selection. These bits select the internal digital loop-back path when the LPBK bit is active (see Register 0x20).

00: Loop back through the front DACs. (Reset default.)

01: Loop back through the surround DACs.

11: Loop back through the center and LFE DACs. (Center DAC loops back from the ADC left channel, the LFE DAC from the

ADC right channel.)

10: Reserved.

SPOVR

SPDIF Override.

0: SPDIF Transmitter is enabled only if the SPDIF pin is pulled low on reset. (Reset default.)

1: SPDIF Transmitter is enabled regardless of the SPDIF pin configuration.

CHEN

Chain Enable. This bit enables chaining of a slave codec SDATA_IN stream into the ID0 pin (Pin 45).

0: Disable chaining. (Reset default.)

1: Enable chaining into ID0 pin.

OMS

Output Microphone Select. This bit will switch the microphone inputs between the MIC1/MIC2 pins and the Center/LFE

pins. This feature is used for those systems that have input/output jack sharing.

Note: See the charts describing the microphone inputs—the description of MS (Bit D8, Register 0x20) and the record

select control register (0x1A).

0: Microphone inputs come from MIC1 and MIC2 pins. Center/LFE outputs behave as expected (default).

1: Microphone inputs now come from the Center/LFE pins. The codec will place the Center/LFE outputs into a High-Z

state—equivalent to setting CLDIS (Bit D11, Register 0x76). Setting the OMS bit, however, will not overwrite the CLDIS;

Center/LFE outputs respond equally to both bits.

DRF

DAC Request Force: This allows the AD1985 to synchronize DAC requests with the AD1981A/ AD1981B.

0: Normal DAC requesting sequence. (Reset default.)

1: Synchronize to AD1981A/B DAC requests.

REGM3

Slave 3 Codec Register Mask.

REGM0

Master Codec Register Mask. (Reset default.)

REGM1

Slave 1 Codec Register Mask.

REGM2

Slave 2 Codec Register Mask.

SLOT16

Enable 16-Bit Slot Mode. SLOT16 makes all AC Link slots 16 bits in length, formatted into 16 slots. This is a preferred mode

for DSP serial port interfacing.