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WM8962B Datasheet(PDF) 115 Page - Wolfson Microelectronics plc

Part # WM8962B
Description  Ultra-Low Power Stereo CODEC with Audio Enhancement DSP, 1W Stereo Class D Speaker Drivers and Ground Referenced Headphone Drivers
PDF  295 Pages
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Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8962B Datasheet(HTML) 115 Page - Wolfson Microelectronics plc

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WM8962
Rev 4.3
115
OUTPUT SIGNAL PATHS ENABLE
The four output mixers, and each analogue output pin and associated PGA, can be independently
enabled or disabled using the register bits described in Table 69.
The Class D speaker drivers are controlled using SPKOUTL_ENA and SPKOUTR_ENA. The
headphone drivers are controlled by HP1L_ENA and HP1R_ENA.
To enable the output PGAs, the reference voltage VMID and the bias current must also be enabled.
See “Reference Voltages and Bias Control” for details of the associated controls VMID_SEL and
BIAS_ENA.
Note that the Speaker and Headphone outputs, the Speaker and Headphone PGAs, and the Speaker
and headphone mixers are all disabled by default. The required signal paths must be enabled and un-
muted using the control bits described in the respective tables below.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R26 (1Ah)
Pwr Mgmt (2)
6
HPOUTL_PGA_E
NA
0
Headphone Left PGA enable
0 = Disabled
1 = Enabled
5
HPOUTR_PGA_E
NA
0
Headphone Right PGA enable
0 = Disabled
1 = Enabled
4
SPKOUTL_PGA_
ENA
0
Speaker Left PGA enable
0 = Disabled
1 = Enabled
3
SPKOUTR_PGA_
ENA
0
Speaker Right PGA enable
0 = Disabled
1 = Enabled
R49 (31h)
Class D
Control (1)
7
SPKOUTR_ENA
0
Right channel class D Speaker
Enable
0 = Disabled
1 = Enabled
6
SPKOUTL_ENA
0
Left channel class D Speaker
Enable
0 = Disabled
1 = Enabled
R69 (45h)
Analogue HP
0
4
HP1L_ENA
0
Enables HP1L input stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set as the final stage of the
HP1L Enable sequence.
0
HP1R_ENA
0
Enables HP1R input stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set as the final stage of the
HP1R Enable sequence.
R99 (63h)
Mixer Enables
3
HPMIXL_ENA
0
Left Headphone Mixer Enable
0 = Disabled
1 = Enabled
2
HPMIXR_ENA
0
Right Headphone Mixer Enable
0 = Disabled
1 = Enabled
1
SPKMIXL_ENA
0
Left Speaker Mixer Enable
0 = Disabled
1 = Enabled
0
SPKMIXR_ENA
0
Right Speaker Mixer Enable
0 = Disabled
1 = Enabled
Table 69 Output Signal Paths Enable



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