WM8962B datasheet(119/295 Pages) WOLFSON

119 / 295 page

WM8962

Rev 4.3

119

SPEAKER OUTPUT PGA CONTROL

There are four speaker output PGAs

– two primary (SPKOUTL and SPKOUTR), and two secondary

(SPKL, SPKR). The speaker outputs are each controlled by a primary PGA and a secondary PGA in

series.

The SPKOUTL and SPKOUTR PGAs give a high degree of control from -68dB to +6dB in 1dB steps.

A detailed table of all SPKOUTL and SPKOUTR gain settings is shown in Table 73. Dedicated

secondary PGAs are provided for each of the SPKOUT output pins. The secondary PGAs provide

control from 0dB to +9dB in 1.5dB steps, and +12dB, on each channel. See Figure 33 for a

representation of this layout.

The direct signal paths from the IN4L and IN4R input pins to the speaker mixers SPKMIXL and

SPKMIXR are enabled using the IN4L_TO_SPKMIXL, IN4L_TO_SPKMIXR, IN4R_TO_SPKMIXL, and

IN4R_TO_SPKMIXR register bits. Each input signal path from IN4 also has an associated PGA with a

gain range from -15dB to +6dB.

To minimise pop and zipper noise, it is recommended that only SPKOUTL PGA and SPKOUTR PGA

are modified while the output signal path is active as these are the only Speaker PGAs with Zero

Cross. In the case of a long period without zero-crossings, a timeout function is provided. When the

zero-cross function is enabled, the volume will update after the timeout period if no earlier zero-cross

has occurred. The timeout clock is enabled using TOCLK_ENA; the timeout period is set by

TOCLK_DIV

. See “Clocking and Sample Rates” for more information on these fields. It is

recommended that the other gain controls on the signal paths should not be modified while the signal

path is active.

The left and right channels on the SPKOUT pins can be boosted using the CLASSD_VOL register.

Note that both left and right channels are updated simultaneously with the CLASSD_VOL register.

The

speaker

output

signal

can

muted

using

the

SPKOUTL_PGA_MUTE

and

SPKOUTR_PGA_MUTE registers. The speaker outputs are un-muted by default.

The SPKOUT_VU bits control the loading of the speaker PGA volume data. When SPKOUT_VU is set

to 0, the volume control data will be loaded into the respective control register, but will not actually

change the gain setting. The left and right Speaker PGA volume settings are both updated when a 1 is

written to any of the SPKOUT_VU bits. This makes it possible to update the gain of the left and right

output paths simultaneously.

The Speaker PGA volume control register fields are described in Table 72.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R40 (28h)

SPKOUTL

volume

SPKOUT_VU

N/A

Speaker Output PGA Volume

Update

Writing a 1 to this bit will update

SPKOUTL_VOL and

SPKOUTR_VOL volumes

simultaneously.

SPKOUTL_ZC

SPKOUTL_VOL (Left Speaker

Output PGA) Zero Cross Enable

0 = Zero cross disabled

1 = Zero cross enabled

6:0

SPKOUTL_VOL [6:0]

00h

(Mute)

Left Speaker Output PGA Volume

000_0000 to 010_1111 = Mute

011_0000 to 011_0101 = -68dB

011_0110 = -67dB

…in 1dB steps

111_1001 = 0dB

…

111_1111 = +6dB

(See Table 73 for output PGA

volume control range)

WM8962B Datasheet(PDF) 119 Page - Wolfson Microelectronics plc

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