WM8962B datasheet(211/295 Pages) WOLFSON

211 / 295 page

WM8962

Rev 4.3

211

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

2:1

SYSCLK_DIV

[1:0]

SYSCLK Divider

00 = MCLK

01 = MCLK / 2

10 = MCLK / 4

11 = Reserved

This field is for read-back only; it is set automatically and

cannot be adjusted.

Note that the division is applied to the selected MCLK

source, including FLL / PLL when applicable.

Protected by security key.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R5 (05h)

ADC & DAC

Control 1

ADCR_DAT_IN

Right ADC Invert

0 = Right ADC output not inverted

1 = Right ADC output inverted

ADCL_DAT_INV

Left ADC Invert

0 = Left ADC output not inverted

1 = Left ADC output inverted

DAC_MUTE_RA

DAC Soft Mute Control

0 = Muting the DAC (DAC_MUTE = 1) will cause the

volume to change immediately to mute.

1 = Muting the DAC (DAC_MUTE = 1) will cause the

volume to ramp down gradually to mute.

DAC_MUTE

Digital DAC Mute

0 = Un-mute

1 = Mute

Note that this bit also exists in R49. Reading or writing to

either location has the same effect.

2:1

DAC_DEEMP

[1:0]

De-Emphasis Control

00 = No de-emphasis

01 = De-emphasis for 32kHz sample rate

10 = De-emphasis for 44.1kHz sample rate

11 = De-emphasis for 48kHz sample rate

ADC_HPF_DIS

ADC High-Pass Filter Disable

0 = Enable

1 = Disable

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R6 (06h)

ADC & DAC

Control 2

13:12

ADC_HPF_SR

[1:0]

ADC High-Pass Filter Sample rate

00 = 8k, 11.025k, 12k

01 = 16k, 22.025k, 24k

10 = 32k, 44.1, 48k

11 = 88.2k, 96k

This field is for read-back only; it is set automatically and

cannot be adjusted.

Protected by security key.

ADC_HPF_MO

ADC High-Pass Filter Mode select

0 = Hi-Fi mode (1st order)

1 = Application mode (2nd order)

WM8962B Datasheet(PDF) 211 Page - Wolfson Microelectronics plc

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