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WM8962B Datasheet(PDF) 210 Page - Wolfson Microelectronics plc |
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WM8962B Datasheet(HTML) 210 Page - Wolfson Microelectronics plc |
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210 / 295 page  WM8962 210 Rev 4.3 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3 (03h) HPOUTR volume 8 HPOUT_VU 0 Headphone Output PGA Volume and Mute Update. Writing 1 to this bit will cause the HPOUTL and HPOUTR volume and mute settings to be updated simultaneously. 7 HPOUTR_ZC 0 HPOUTR_VOL (Right Headphone Output PGA) Zero Cross Enable 0 = Zero cross disabled 1 = Zero cross enabled 6:0 HPOUTR_VOL [6:0] 000_0000 Right Headphone Output PGA Volume 000_0000 to 010_1111 = Mute 011_0000 to 011_0101 = -68dB 011_0110 = -67dB …in 1dB steps 111_1001 = 0dB … 111_1111 = +6dB Register 03h HPOUTR volume REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R4 (04h) Clocking1 10:9 DSPCLK_DIV [1:0] 00 DSP Clock Divider 00 = MCLK 01 = MCLK / 2 10 = MCLK / 4 11 = Reserved This field is for read-back only; it is set automatically and cannot be adjusted. Protected by security key. 8:6 ADCSYS_CLK_ DIV [2:0] 000 ADC Sample Rate Divider 000 = SYSCLK 001 = Reserved 010 = SYSCLK / 2 011 = SYSCLK / 3 100 = SYSCLK / 4 101 = Reserved 110 = SYSCLK / 6 111= Reserved This field is for read-back only; it is set automatically and cannot be adjusted. Protected by security key. 5:3 DACSYS_CLK_ DIV [2:0] 100 DAC Sample Rate Divider 000 = SYSCLK 001 = Reserved 010 = SYSCLK / 2 011 = SYSCLK / 3 100 = SYSCLK / 4 101 = Reserved 110 = SYSCLK / 6 111= Reserved This field is for read-back only; it is set automatically and cannot be adjusted. Protected by security key. |
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