PC87393 datasheet(31/148 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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2.2.4

Standard Configuration Registers

Figure 3. Conﬁguration Register Map

SuperI/O Control and Conﬁguration Registers

The SuperI/O configuration registers at indexes 20h and 27h are mainly used for part identification, global power manage-

ment and the selection of pin multiplexing options. For details, see Section 2.10.

Logical Device Control and Conﬁguration Registers

A subset of these registers is implemented for each logical device. See functional block descriptions in the following sections.

Control

The only implemented control register for each logical device is the Activate register at index 30h. Bit 0 of the Activate reg-

ister controls the activation of the associated functional block. Activation enables access to the functional block’s registers,

and attaches its system resources, which are unassigned as long as it is not activated. Other effects may apply, on a func-

tion-specific basis (such as clock enable and active pinout signaling).

Standard Conﬁguration

The standard configuration registers manage the PnP resource allocation to the functional blocks. The I/O port base address

descriptor 0 is a pair of registers at Index 60-61h, holding the first 16-bit base address for the register set of the functional

block. An optional 16-bit second base-address (descriptor 1) at index 62-63h is used for logical devices with more than one

SuperI/O Control and

Conﬁguration Registers

Logical Device Control and

one per Logical Device

Conﬁguration Registers -

Index

07h

Logical Device Number

20h

SuperI/O ID

21h

SuperI/O Conﬁguration 1

22h

SuperI/O Conﬁguration 2

23h

SuperI/O Conﬁguration 3

24h

SuperI/O Conﬁguration 4

25h

SuperI/O Conﬁguration 5

26h

SuperI/O Conﬁguration 6

27h

SuperI/O Revision ID

28h

SuperI/O Conﬁguration 8

29h

SuperI/O Conﬁguration 9

2Ah

SuperI/O Conﬁguration A

2Bh - 2Eh

Reserved exclusively for National use

30h

Logical Device Control (Activate)

60h

I/O Base Address Descriptor 0 Bits 15-8

61h

I/O Base Address Descriptor 0 Bits 7-0

70h

Interrupt Number and Wake-Up on IRQ Enable

71h

IRQ Type Select

74h

DMA Channel Select 0

75h

DMA Channel Select 1

F0h - F9h

Device Speciﬁc Logical Device Conﬁguration 1 to 10

(some are optional)

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