PC87393 datasheet(36/148 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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2.7

PROTECTION

The PC8739x provides features to protect the PC at software levels. It can be locked to protect configuration bits or alteration

of the device hardware configuration, as well as internal GPIO settings and several types of configuration settings.

All protection mechanisms can be used optionally.

2.7.1

Pin Configuration Lock

To lock the pin configuration of the PC8739x in order to prevent unwanted changes to hardware configuration, set bit 7 of

the SIOCF1 register to 1. This causes all function select configuration bits to become read only bits. This bit can only be

cleared by a hardware reset.

2.7.2

GPIO Pin Function Lock

The PC8739x is capable of locking the attributes of each GPIO pin. The following attributes can be locked:

Output enable

Output type

Static pull-up

Driven data.

GPIO pins are locked per pin by setting the Lock bit in the appropriate GPIO Pin Configuration register. When the Lock bit

is set, the configuration of the associated GPIO pin can be cleared only by a hardware reset.

2.8

LPC INTERFACE

2.8.1

LPC Transactions Supported

The PC8739x LPC interface can respond to the following LPC transactions as part of the standard SuperI/O implementation:

— I/O read and write cycles

— 8-bit DMA read and write cycles

— DMA request cycles.

In addition, the X-Bus bridge uses the following transaction:

— 8-bit memory read and write (PC87393 and PC87393F only)

— 8-bit FWH read and write (PC87393F only)

LPC transactions conform with Intel’s

LPC Interface Specification, Revision 1.00.

The LPC-FWH read and write cycles are similar to memory read and write cycles. The specifications of these cycles are

listed below. The Address, Data, TAR and SYNC cycles are as specified for LPC memory read and write cycles. The START

and ID fields are similar to the equivalent cycle in LPC memory read and write cycles but differ in the data placed on the LAD

signals (see details in the cycle description).

FWH Read Cycle (PC87393F only)

1. START:

1101

(0xD)

2. ID field:

FWH ID nibble (compared with bits 7-4 of X-Bus Memory Configuration Register, Section 2.19.8)

3. Address: 8 address nibbles (MS nibble first; see usage below)

4. TAR (two cycles)

5. SYNC

6. DATA:

2 data nibbles (LS nibble first; D3-D0, D7-D4)

7. TAR (two cycles)

FWH Write Cycle (PC87393F only)

1. START:

1110 (0xE)

2. ID field:

FWH ID nibble (compared with bits 7-4 of X-Bus Memory Configuration Register, Section 2.19.8)

3. Address: 8 address nibbles (MS nibble first; see usage below)

4. DATA:

2 data nibbles (LS nibble first; D3-D0, D7-D4)

5. TAR (two cycles)

6. SYNC

7. TAR (two cycles)

The ID field is compared with bits 7-4 of the X-Bus Memory Configuration register, described in Section 2.19.8. If the two

match, the PC8739x continues handling the transaction; if not, the current LPC-FWH transaction is ignored.

PC87393 Datasheet(PDF) 36 Page - National Semiconductor (TI)

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