PC87393 datasheet(50/148 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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2.12 PARALLEL PORT CONFIGURATION

2.12.1

General Description

The PC8739x Parallel Port supports all IEEE1284 standard communication modes: Compatibility (known also as Standard

or SPP), Bidirectional (known also as PS/2), FIFO, EPP (known also as Mode 4) and ECP (with an optional Extended ECP

mode).

The Parallel Port includes two groups of runtime registers, as follows:

• A group of 21 registers at first level offset, sharing 14 entries. Three of this registers (at offsets 403h, 404h and 405h)

are used only in the Extended ECP mode.

• A group of four registers, used only in the Extended ECP mode, accessed by a second level offset.

The desired mode is selected by the ECR runtime register (offset 402h). The selected mode determines which runtime reg-

isters are used and which address bits are used for the base address. See Tables 18 and 19 for a listing of all registers, their

offset addresses, and the associated modes.

Table 18. Parallel Port Registers at First Level Offset

Offset

Mnemonic

Mode(s)

Type

00h

DATAR

0,1

R/W

Data

AFIFO

ECP FIFO (Address)

DTR

R/W

Data (for EPP)

01h

DSR

0,1,2,3

Status

STR

Status (for EPP)

02h

DCR

0,1,2,3

R/W

Control

CTR

R/W

Control (for EPP)

03h

ADDR

R/W

EPP Address

04h

DATA0

R/W

EPP Data Port 0

05h

DATA1

R/W

EPP Data Port 1

06h

DATA2

R/W

EPP Data Port 2

07h

DATA3

R/W

EPP Data Port 3

400h

CFIFO

DFIFO

TFIFO

CNFGA

R/W

PP Data FIFO

ECP Data FIFO

Test FIFO

Conﬁguration A

401h

CNFGB

Conﬁguration B

402h

ECR

0,1,2,3

R/W

Extended Control

403h

EIR1

These registers are extended to the standard IEEE1284 registers. They

are accessible only when enabled by bit 4 of the Parallel Port Conﬁgura-

tion register (see Section 2.12.3).

0,1,2,3

R/W

Extended Index

404h

EDR1

0,1,2,3

R/W

Extended Data

405h

EAR1

0,1,2,3

R/W

Extended Auxiliary Status

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