PC87393 datasheet(81/148 Pages) NSC

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4.0 WATCHDOG Timer (WDT) (Continued)

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4.3

WATCHDOG TIMER REGISTERS

The WATCHDOG Timer registers at offsets 00h-02h relative to the WATCHDOG base address, are shown in the following

set.

The following abbreviations are used to indicate the Register Type:

R/W

= Read/Write

= Read from a specific address returns the value of a specific register. Write to the same address is to a different register.

= Write

= Read Only

R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.

4.3.1

WATCHDOG Timer Register Map

4.3.2

WATCHDOG Timeout Register (WDTO)

This register holds the programmable timeout period, between 1 and 255 minutes. Writing to this register de-asserts the

WDO output and sets the WDO status bit to 1 (inactive). Additionally, writing to this register is interpreted as a command for

starting or stopping the WATCHDOG Timer, according to the data written. If a non-zero value is written, the timer is activated

(countdown starts). If a non-zero value is written when the counter is running, the timer is immediately reloaded with the new

value and starts counting down from the new value. If 00h is written, the timer and its outputs are de-activated.

Location:

Offset 00h

Type:

R/W

Offset Mnemonic

Type

Section

00h

WDTO

WATCHDOG Timeout

R/W

4.3.2

01h

WDMSK

WATCHDOG Mask

R/W

4.3.3

02h

WDST

WATCHDOG Status

4.3.4

03h

Reserved

Bit

76543210

Name

Programmed Timeout Period

Reset

00000000

Bit

Description

7-0

Programmed Timeout Period. These bits hold the binary value of the timeout period in minutes (1 to 255). A

value of 00h halts the counter and forces the outputs to inactive levels. A device reset clears the register to 00h.

00h: Timer and WDO outputs inactive

01h-FFh: Programmed timeout period (in minutes)

PC87393 Datasheet(PDF) 81 Page - National Semiconductor (TI)

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