PC87393 datasheet(62/148 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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2.17 GAME PORT (GMP) CONFIGURATION

This section applies to the PC87393 and PC87393F only.

2.17.1

Logical Device 11 (GMP) Configuration

Table 26 lists the configuration registers which affect the Game Port. Only the last register (F0h) is described here. See Sec-

tions 2.2.3 and 2.2.4 for a detailed description of the others.

Table 26. GMP Conﬁguration Registers

2.17.2

Game Port Configuration Register

This register is reset by hardware to 00h.

Location:

Index F0h

Type:

R/W

Index

Conﬁguration Register or Action

Type

Reset

30h

Activate. When bit 0 is cleared, the registers of this logical device are not

accessible.

R/W

00h

60h

Base Address MSB register

R/W

02h

61h

Base Address LSB register.

R/W

01h

70h

Interrupt Number and Wake-Up on IRQ Enable register.

R/W

00h

71h

Interrupt Type. Bit 1 is read/write. Other bits are read only.

R/W

03h

74h

Report no DMA assignment

04h

75h

Report no DMA assignment

04h

F0h

Game Port Conﬁguration register

R/W

00h

Bit

7654

210

Name

Reserved

GMP

Enhanced

Mode Enable

Internal

Pull-Up

Enable

Reserved

TRI-STATE

Control

Reset

0000

000

Bit

Description

7-4

Reserved

GMP Enhanced Mode Enable. See Usage Hints below.

0: Disabled (default)

1: Enabled

Internal Pull-Up Enable. When the GMP functions are selected, this bit controls the internal pull-up resistor on

pins 96 (GPIO07/JOYABTN0), 3 (GPIO00/JOYABTN1), 97 (GPIO06/JOYBBTN0) and 2 (GPIO01/JOYBBTN1) or

pins 74 (GPIO17/JOYABTN0), 81 (GPIO10/JOYABTN1), 75 (GPIO16/JOYBBTN0), 80 (GPIO11/JOYBBTN1).

0: Disabled (default)

1: Enabled

Reserved

TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.

0: Disabled (default)

1: Enabled

PC87393 Datasheet(PDF) 62 Page - National Semiconductor (TI)

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