PC87393 datasheet(88/148 Pages) NSC

88 / 148 page

5.0 Game Port (GMP) (Continued)

www.national.com

5.3.2

Game Port Control Register (GMPCTL)

This register affects the functionality of the Game Port only when operated in Enhanced mode (bit 0 of this register is set

to 1). Bits 1,2 and 4-7 affect Game Port functionality, as described in the table below.

Location:

Offset 00h

Type:

R/W

Bit

76543210

Name

Device B

Button 1

Debounce

Enable

Device B

Button 0

Debounce

Enable

Device A

Button 1

Debounce

Enable

Device A

Button 0

Debounce

Enable

Reserved

Device B

Pre-Scale

Enable

Device A

Pre-Scale

Enable

GMP

Enhanced

Mode

Enable

Reset

00000000

Required

Bit

Description

Device B Button 1 Debounce Enable. When set to 1, enables a 16 ms input debouncer on Device B Button 1

status input.

0: Disabled (default)

1: Enabled

Device B Button 0 Debounce Enable. Same as bit 7, but for Device B Button 0.

0: Disabled (default)

1: Enabled

Device A Button 1 Debounce Enable. Same as bit 7, but for Device A Button 1.

0: Disabled (default)

1: Enabled

Device A Button 0 Debounce Enable. Same as bit 7, but for Device A Button 0.

0: Disabled (default)

1: Enabled

Reserved

Device B Pre-Scale Enable. This bit determines the clock frequency used by Device B position counters.

0: 1 MHz (default)

1: 500 KHz

Device A Pre-Scale Enable. This bit determines the clock frequency used by Device A position counters.

0: 1 MHz (default)

1: 500 KHz

GMP Enhanced Mode Enable

0: Disabled (default)

1: Enabled

PC87393 Datasheet(PDF) 88 Page - National Semiconductor (TI)

PC87393 Datasheet(HTML) 88 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL